uqsub

Vector Unsigned Saturating Subtract

UQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Subtracts unsigned integers with saturation.

Details

Vector Unsigned Saturating Subtract subtracts corresponding unsigned integer elements from two NEON registers with saturation, placing the difference into the destination register. If the subtraction would produce a negative result, the result is saturated to zero. This instruction operates element-wise on all vector elements and does not modify the condition flags. AArch64-only NEON instruction with no privilege restrictions.

Pseudocode Operation

for i = 0 to elements_in_vector(Q, size) - 1 do
  if Vn[i] < Vm[i] then
    Vd[i] ← 0
  else
    Vd[i] ← Vn[i] - Vm[i]
  end if
end for

Example

UQSUB v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout
0
Q
1
01110
size
1
Rm
00101
1
Rn
Rd
 
Format SIMD Three Register
Opcode 0x2E202C00
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x7E202C00 UQSUB <V><d>, <V><n>, <V><m> A64 01 | 1 | 11110 | size | 1 | Rm | 00101 | 1 | Rn | Rd
0x2E202C00 UQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 1 | 01110 | size | 1 | Rm | 00101 | 1 | Rn | Rd
0x441B8000 UQSUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 01000100 | size | 011 | 0 | 1 | 1 | 100 | Pg | Zm | Zdn
0x2527C000 UQSUB <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>} A64 00100101 | size | 100 | 11 | 1 | 11 | sh | imm8 | Zdn
0x04201C00 UQSUB <Zd>.<T>, <Zn>.<T>, <Zm>.<T> A64 00000100 | size | 1 | Zm | 000 | 11 | 1 | Zn | Zd

Description

Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;
integer element1;
integer element2;
integer diff;
boolean sat;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    diff = element1 - element2;
    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
    if sat then FPSR.QC = '1';

V[d, datasize] = result;