vmov

Vector Move (Immediate)

VMOV<c>.<dt> <Qd>, #<imm>

Moves immediate value into vector.

Details

Vector Move (Immediate) moves an immediate value into all elements of a 128-bit NEON register. The immediate is replicated across elements according to the data type (8, 16, 32, or 64 bits) and element expansion mode (cmode). No flags are affected. This is a NEON instruction available in both A32 and T32 states when NEON is supported.

Pseudocode Operation

imm_expanded ← ExpandImmediate(imm, cmode)
for each element i in Qd:
  Qd[i] ← imm_expanded

Example

VMOV.dt q0, #16

Encoding

Binary Layout
1111001
i
1
D
000
imm3
Vd
cmode
0
0
0
1
imm4
 
Format NEON Imm
Opcode 0xF2800010
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • imm
    Value

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0C400B10 VMOV{<c>}{<q>} <Dm>, <Rt>, <Rt2> A32 cond | 11000 | 1 | 0 | 0 | Rt2 | Rt | 10 | 11 | 00 | M | 1 | Vm
0x0C500B10 VMOV{<c>}{<q>} <Rt>, <Rt2>, <Dm> A32 cond | 11000 | 1 | 0 | 1 | Rt2 | Rt | 10 | 11 | 00 | M | 1 | Vm
0xEC400B10 VMOV{<c>}{<q>} <Dm>, <Rt>, <Rt2> T32 111011000 | 1 | 0 | 0 | Rt2 | Rt | 10 | 11 | 00 | M | 1 | Vm
0xEC500B10 VMOV{<c>}{<q>} <Rt>, <Rt2>, <Dm> T32 111011000 | 1 | 0 | 1 | Rt2 | Rt | 10 | 11 | 00 | M | 1 | Vm
0x0E000910 VMOV{<c>}{<q>}.F16 <Sn>, <Rt> A32 cond | 1110000 | 0 | Vn | Rt | 1001 | N | 0 | 0 | 1 | 0 | 0 | 0 | 0
0x0E100910 VMOV{<c>}{<q>}.F16 <Rt>, <Sn> A32 cond | 1110000 | 1 | Vn | Rt | 1001 | N | 0 | 0 | 1 | 0 | 0 | 0 | 0
0xEE000910 VMOV{<c>}{<q>}.F16 <Sn>, <Rt> T32 11101110000 | 0 | Vn | Rt | 1001 | N | 0 | 0 | 1 | 0 | 0 | 0 | 0
0xEE100910 VMOV{<c>}{<q>}.F16 <Rt>, <Sn> T32 11101110000 | 1 | Vn | Rt | 1001 | N | 0 | 0 | 1 | 0 | 0 | 0 | 0
0xF2800010 VMOV{<c>}{<q>}.I32 <Dd>, #<imm> A32 1111001 | i | 1 | D | 000 | imm3 | Vd | cmode | 0 | 0 | 0 | 1 | imm4
0xF2800050 VMOV{<c>}{<q>}.I32 <Qd>, #<imm> A32 1111001 | i | 1 | D | 000 | imm3 | Vd | cmode | 0 | 1 | 0 | 1 | imm4
0x0EB00900 VMOV{<c>}{<q>}.F16 <Sd>, #<imm> A32 cond | 11101 | D | 11 | imm4H | Vd | 10 | 01 | 0 | 0 | 0 | 0 | imm4L
0x0EB00A00 VMOV{<c>}{<q>}.F32 <Sd>, #<imm> A32 cond | 11101 | D | 11 | imm4H | Vd | 10 | 10 | 0 | 0 | 0 | 0 | imm4L
0x0EB00B00 VMOV{<c>}{<q>}.F64 <Dd>, #<imm> A32 cond | 11101 | D | 11 | imm4H | Vd | 10 | 11 | 0 | 0 | 0 | 0 | imm4L
0xF2800810 VMOV{<c>}{<q>}.I16 <Dd>, #<imm> A32 1111001 | i | 1 | D | 000 | imm3 | Vd | cmode | 0 | 0 | 0 | 1 | imm4

Description

Copy immediate value to a SIMD&FP register places an immediate constant into every element of the destination register. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDOrVFPEnabled(TRUE, advsimd);
    if single_register then
        S[d] = imm32;
    else
        for r = 0 to regs-1
            D[d+r] = imm64;