sm3ss1

SM3 Step 1 (A32)

SM3SS1.32 <Qd>, <Qn>, <Qm>

SM3 cryptographic hash step 1.

Pseudocode Operation

Qd ← SM3_StepSS1(Qn, Qm)

Example

SM3SS1.32 q0, q1, q2

Encoding

Binary Layout

110011100

31:23

22:21

20:16

14:10

9:5

4:0

Format Crypto 3-Reg

Opcode 0xCE400000

Extension Crypto (SM3)

Operands

Qd
Destination 128-bit SIMD register
Qn
First source 128-bit SIMD register
Qm
Second source 128-bit SIMD register

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xCE400000	SM3SS1 <Vd>.4S, <Vn>.4S, <Vm>.4S, <Va>.4S		A64		110011100 \| 10 \| Rm \| 0 \| Ra \| Rn \| Rd

Description

SM3SS1 rotates the top 32 bits of the 128-bit vector in the first source SIMD&FP register by 12, and adds that 32-bit value to the two other 32-bit values held in the top 32 bits of each of the 128-bit vectors in the second and third source SIMD&FP registers, rotating this result left by 7 and writing the final result into the top 32 bits of the vector in the destination SIMD&FP register, with the bottom 96 bits of the vector being written to 0. This instruction is implemented only when FEAT_SM3 is implemented.

Operation

AArch64.CheckFPAdvSIMDEnabled();

bits(128) Vm = V[m, 128];
bits(128) Vn = V[n, 128];
bits(128) Va = V[a, 128];
bits(128) result;
result<127:96> = ROL((ROL(Vn<127:96>, 12) + Vm<127:96> + Va<127:96>), 7);
result<95:0> = Zeros(96);
V[d, 128] = result;