mrc

Move to Register from Coprocessor (A32)

MRC<c> <coproc>, <opc1>, <Rt>, <CRn>, <CRm>{, <opc2>}

Reads a coprocessor register into a general-purpose register.

Details

Moves data from a coprocessor register (typically CP15 for system control) into a general-purpose register. The instruction is conditional and executes only if the condition code is satisfied. The N, Z, C, V flags may be modified depending on the coprocessor register being read. This is an A32-only instruction with implementation-specific behavior depending on the source coprocessor register.

Pseudocode Operation

if ConditionPassed(cond) then
  Rt ← CP[coproc, opc1, CRn, CRm, opc2]
  condition_flags may be updated by coprocessor

Example

MRC p15, 0, r3, c1, c2

Encoding

Binary Layout
cond
1110
opc1
1
CRn
Rt
111
coproc<0>
opc2
1
CRm
 
Format Coprocessor
Opcode 0x0E100E10
Extension A32 (System)

Operands

  • coproc
    CP Num
  • Rt
    Transfer general-purpose register (load/store)
  • CRn
    Src CP Reg

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0E100E10 MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} A32 cond | 1110 | opc1 | 1 | CRn | Rt | 111 | coproc<0> | opc2 | 1 | CRm
0xEE100E10 MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} T32 11101110 | opc1 | 1 | CRn | Rt | 111 | coproc<0> | opc2 | 1 | CRm

Description

Move to general-purpose register from System register. This instruction copies the value of a System register to a general-purpose register. The System register descriptions identify valid encodings for this instruction. Other encodings are undefined. For more information see About the AArch32 System register interface and General behavior of System registers. In an implementation that includes EL2, MRC accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MRC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see EL2 configurable instruction enables, disables, and traps. Because of the range of possible traps to Hyp mode, the MRC pseudocode does not show these possible traps.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();

    if t != 15 || AArch32.SysRegReadCanWriteAPSR(cp, ThisInstr()) then
        AArch32.SysRegRead(cp, ThisInstr(), t);
    else
        UNPREDICTABLE;