vcvt

Vector Convert (Float to Integer)

VCVT<c>.<Td>.<Tm> <Sd>, <Sm>

Converts float to signed/unsigned integer.

Details

Converts a single-precision floating-point value to a signed or unsigned 32-bit integer and stores the result in Sd. This VFP instruction performs floating-point-to-integer conversion with rounding behavior controlled by the FPSCR rounding mode. The condition flags are not updated; conversion errors (overflow, invalid operand) may set exception bits in the FPSCR depending on exception configuration. Execution is conditional based on the <c> condition code and requires VFP extension support in A32/T32 modes.

Pseudocode Operation

result ← Convert_F32_to_Int32(Sm, signed/unsigned, rounding_mode)
Sd ← result
if (overflow or invalid) then FP_Exception_or_Saturate()

Example

VCVT.Td.Tm s0, s2

Encoding

Binary Layout
cond
11101
D
11
1
000
Vd
10
01
op
1
M
0
Vm
 
Format VFP Convert
Opcode 0x0EB80940
Extension VFP (Float)

Operands

  • Sd
    Destination 32-bit floating-point register
  • Sm
    Second source 32-bit floating-point register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF3B60640 VCVT{<c>}{<q>}.BF16.F32 <Dd>, <Qm> A32 111100111 | D | 11 | 01 | 10 | Vd | 0 | 1100 | 1 | M | 0 | Vm
0xFFB60640 VCVT{<c>}{<q>}.BF16.F32 <Dd>, <Qm> T32 111111111 | D | 11 | 01 | 10 | Vd | 0 | 1100 | 1 | M | 0 | Vm
0x0EB70AC0 VCVT{<c>}{<q>}.F64.F32 <Dd>, <Sm> A32 cond | 11101 | D | 11 | 0 | 111 | Vd | 10 | size | 1 | 1 | M | 0 | Vm
0x0EB70AC0 VCVT{<c>}{<q>}.F32.F64 <Sd>, <Dm> A32 cond | 11101 | D | 11 | 0 | 111 | Vd | 10 | size | 1 | 1 | M | 0 | Vm
0xEEB70AC0 VCVT{<c>}{<q>}.F64.F32 <Dd>, <Sm> T32 111011101 | D | 11 | 0 | 111 | Vd | 10 | size | 1 | 1 | M | 0 | Vm
0xEEB70AC0 VCVT{<c>}{<q>}.F32.F64 <Sd>, <Dm> T32 111011101 | D | 11 | 0 | 111 | Vd | 10 | size | 1 | 1 | M | 0 | Vm
0xF3B20700 VCVT{<c>}{<q>}.F32.F16 <Qd>, <Dm> A32 111100111 | D | 11 | size | 10 | Vd | 0 | 11 | 1 | 0 | 0 | M | 0 | Vm
0xF3B20600 VCVT{<c>}{<q>}.F16.F32 <Dd>, <Qm> A32 111100111 | D | 11 | size | 10 | Vd | 0 | 11 | 0 | 0 | 0 | M | 0 | Vm
0xFFB20700 VCVT{<c>}{<q>}.F32.F16 <Qd>, <Dm> T32 111111111 | D | 11 | size | 10 | Vd | 0 | 11 | 1 | 0 | 0 | M | 0 | Vm
0xFFB20600 VCVT{<c>}{<q>}.F16.F32 <Dd>, <Qm> T32 111111111 | D | 11 | size | 10 | Vd | 0 | 11 | 0 | 0 | 0 | M | 0 | Vm
0xF3B30600 VCVT{<c>}{<q>}.<dt1>.<dt2> <Dd>, <Dm> A32 111100111 | D | 11 | size | 11 | Vd | 0 | 11 | op | 0 | M | 0 | Vm
0xF3B30640 VCVT{<c>}{<q>}.<dt1>.<dt2> <Qd>, <Qm> A32 111100111 | D | 11 | size | 11 | Vd | 0 | 11 | op | 1 | M | 0 | Vm
0xFFB30600 VCVT{<c>}{<q>}.<dt1>.<dt2> <Dd>, <Dm> T32 111111111 | D | 11 | size | 11 | Vd | 0 | 11 | op | 0 | M | 0 | Vm
0xFFB30640 VCVT{<c>}{<q>}.<dt1>.<dt2> <Qd>, <Qm> T32 111111111 | D | 11 | size | 11 | Vd | 0 | 11 | op | 1 | M | 0 | Vm

Description

Convert integer to floating-point converts a 32-bit integer to floating-point using the rounding mode specified by the FPSCR, and places the result in a second register. VCVT (between floating-point and fixed-point, floating-point) describes conversions between floating-point and 16-bit integers. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckVFPEnabled(TRUE);
    if to_integer then
        case esize of
            when 16
                S[d] = FPToFixed(S[m]<15:0>, 0, unsigned, FPSCR[], rounding, 32);
            when 32
                S[d] = FPToFixed(S[m], 0, unsigned, FPSCR[], rounding, 32);
            when 64
                S[d] = FPToFixed(D[m], 0, unsigned, FPSCR[], rounding, 32);
    else
        case esize of
            when 16
                bits(16) fp16 = FixedToFP(S[m], 0, unsigned, FPSCR[], rounding, 16);
                S[d] = Zeros(16):fp16;
            when 32
                S[d] = FixedToFP(S[m], 0, unsigned, FPSCR[], rounding, 32);
            when 64
                D[d] = FixedToFP(S[m], 0, unsigned, FPSCR[], rounding, 64);