qadd16

Saturating Add 16

QADD16<c> <Rd>, <Rn>, <Rm>

Parallel saturating add of 2 signed halfwords.

Details

Performs parallel saturating addition of two signed 16-bit halfwords in Rn and Rm, storing results in Rd. Each halfword is independently saturated to the signed 16-bit range [−32768, 32767] if overflow occurs. No condition flags are affected. Execution restricted to A32 with DSP extension; requires ARMv6 or later.

Pseudocode Operation

Rd[31:16] ← SignedSat(Rn[31:16] + Rm[31:16], 16)
Rd[15:0] ← SignedSat(Rn[15:0] + Rm[15:0], 16)

Example

QADD16 r0, r1, r2

Encoding

Binary Layout
cond
01100
010
Rn
Rd
1
1
1
1
0
00
1
Rm
 
Format SIMD Integer
Opcode 0x06200F10
Extension A32 (DSP)

Operands

  • Rd
    Destination general-purpose register
  • Rn
    First source / base general-purpose register
  • Rm
    Second source / offset general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x06200F10 QADD16{<c>}{<q>} {<Rd>,} <Rn>, <Rm> A32 cond | 01100 | 010 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 00 | 1 | Rm
0xFA90F010 QADD16{<c>}{<q>} {<Rd>,} <Rn>, <Rm> T32 111110101 | 001 | Rn | 1111 | Rd | 0 | 0 | 0 | 1 | Rm

Description

Saturating Add 16 performs two 16-bit integer additions, saturates the results to the 16-bit signed integer range -215 <= x <= 215 - 1, and writes the results to the destination register.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    sum1 = SInt(R[n]<15:0>) + SInt(R[m]<15:0>);
    sum2 = SInt(R[n]<31:16>) + SInt(R[m]<31:16>);
    R[d]<15:0>  = SignedSat(sum1, 16);
    R[d]<31:16> = SignedSat(sum2, 16);