qadd16

Saturating Add 16

QADD16<c> <Rd>, <Rn>, <Rm>

Parallel saturating add of 2 signed halfwords.

Pseudocode Operation

Rd[31:16] ← SignedSat(Rn[31:16] + Rm[31:16], 16)
Rd[15:0] ← SignedSat(Rn[15:0] + Rm[15:0], 16)

Example

QADD16 r0, r1, r2

Encoding

Binary Layout

cond

31:28

01100

27:23

010

22:20

Rn

19:16

Rd

15:12

1

11

1

10

1

9

1

8

0

7

00

6:5

1

4

Rm

3:0

 

Format SIMD Integer

Opcode 0x06200F10

Extension A32 (DSP)

Operands

• Rd
  Destination general-purpose register
• Rn
  First source / base general-purpose register
• Rm
  Second source / offset general-purpose register

Related

More in A32 (DSP)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x06200F10	QADD16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>		A32		cond | 01100 | 010 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 00 | 1 | Rm
0xFA90F010	QADD16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>		T32		111110101 | 001 | Rn | 1111 | Rd | 0 | 0 | 0 | 1 | Rm

Description

Saturating Add 16 performs two 16-bit integer additions, saturates the results to the 16-bit signed integer range -215 <= x <= 215 - 1, and writes the results to the destination register.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    sum1 = SInt(R[n]<15:0>) + SInt(R[m]<15:0>);
    sum2 = SInt(R[n]<31:16>) + SInt(R[m]<31:16>);
    R[d]<15:0>  = SignedSat(sum1, 16);
    R[d]<31:16> = SignedSat(sum2, 16);