shadd16

Signed Halving Add 16

SHADD16<c> <Rd>, <Rn>, <Rm>

Signed add and halving (average) of 2 halfwords.

Details

The Signed Halving Add 16 instruction signed add and halving (average) of 2 halfwords.

Pseudocode Operation

Rd ← Rn + Rm
// Flags affected: N, Z, C, V

Example

SHADD16 r0, r1, r2

Encoding

Binary Layout
cond
01100011
Rn
Rd
1111
0001
Rm
 
Format SIMD Integer
Opcode 0x06300F10
Extension A32 (DSP)

Operands

  • Rd
    Destination general-purpose register
  • Rn
    First source / base general-purpose register
  • Rm
    Second source / offset general-purpose register