ldr

Load SIMD&FP Register (Immediate)

LDR <Bt|Ht|St|Dt|Qt>, [<Xn|SP>, #<pimm>]

Loads a floating-point/SIMD register from memory.

Pseudocode Operation

Vt ← Memory[address]

Example

LDR Qt, [x1, #16]

Encoding

Binary Layout

10

31:30

111

29:27

1

26

01

25:24

01

23:22

imm12

21:10

Rn

9:5

Rt

4:0

 

Format Load/Store

Opcode 0xBD400000

Extension Floating Point

Operands

• Bt|Ht|St|Dt|Qt
  Transfer SIMD&FP register (byte, half, single, double or quad-precision)
• Xn|SP
  First source / base 64-bit integer register
• pimm
  Positive immediate offset

Related

Other forms of ldr

• ldr Load Register (Immediate)
• ldr Load Register (Literal)
• ldr Load Register (Register)
• ldr Load Register PC-Relative (A32)
• ldr Load Register PC-Relative (Thumb)
• ldr Load Register (A32 Immediate)

More in Floating Point

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x3C400400	LDR <Bt>, [<Xn|SP>], #<simm>		A64		00 | 111 | 1 | 00 | 01 | 0 | imm9 | 01 | Rn | Rt
0x7C400400	LDR <Ht>, [<Xn|SP>], #<simm>		A64		01 | 111 | 1 | 00 | 01 | 0 | imm9 | 01 | Rn | Rt
0xBC400400	LDR <St>, [<Xn|SP>], #<simm>		A64		10 | 111 | 1 | 00 | 01 | 0 | imm9 | 01 | Rn | Rt
0xFC400400	LDR <Dt>, [<Xn|SP>], #<simm>		A64		11 | 111 | 1 | 00 | 01 | 0 | imm9 | 01 | Rn | Rt
0x3CC00400	LDR <Qt>, [<Xn|SP>], #<simm>		A64		00 | 111 | 1 | 00 | 11 | 0 | imm9 | 01 | Rn | Rt
0x3C400C00	LDR <Bt>, [<Xn|SP>, #<simm>]!		A64		00 | 111 | 1 | 00 | 01 | 0 | imm9 | 11 | Rn | Rt
0x7C400C00	LDR <Ht>, [<Xn|SP>, #<simm>]!		A64		01 | 111 | 1 | 00 | 01 | 0 | imm9 | 11 | Rn | Rt
0xBC400C00	LDR <St>, [<Xn|SP>, #<simm>]!		A64		10 | 111 | 1 | 00 | 01 | 0 | imm9 | 11 | Rn | Rt
0xFC400C00	LDR <Dt>, [<Xn|SP>, #<simm>]!		A64		11 | 111 | 1 | 00 | 01 | 0 | imm9 | 11 | Rn | Rt
0x3CC00C00	LDR <Qt>, [<Xn|SP>, #<simm>]!		A64		00 | 111 | 1 | 00 | 11 | 0 | imm9 | 11 | Rn | Rt
0x3D400000	LDR <Bt>, [<Xn|SP>{, #<pimm>}]		A64		00 | 111 | 1 | 01 | 01 | imm12 | Rn | Rt
0x7D400000	LDR <Ht>, [<Xn|SP>{, #<pimm>}]		A64		01 | 111 | 1 | 01 | 01 | imm12 | Rn | Rt
0xBD400000	LDR <St>, [<Xn|SP>{, #<pimm>}]		A64		10 | 111 | 1 | 01 | 01 | imm12 | Rn | Rt
0xFD400000	LDR <Dt>, [<Xn|SP>{, #<pimm>}]		A64		11 | 111 | 1 | 01 | 01 | imm12 | Rn | Rt

Description

Load SIMD&FP Register (immediate offset). This instruction loads an element from memory, and writes the result as a scalar to the SIMD&FP register. The address that is used for the load is calculated from a base register value, a signed immediate offset, and an optional offset that is a multiple of the element size. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();
bits(64) address;
bits(datasize) data;

AccessDescriptor accdesc = CreateAccDescASIMD(memop, FALSE, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

if !postindex then
    address = GenerateAddress(address, offset, accdesc);

case memop of
    when MemOp_STORE
        data = V[t, datasize];
        Mem[address, datasize DIV 8, accdesc] = data;

    when MemOp_LOAD
        data = Mem[address, datasize DIV 8, accdesc];
        V[t, datasize] = data;

if wback then
    if postindex then
        address = GenerateAddress(address, offset, accdesc);
    if n == 31 then
        SP[] = address;
    else
        X[n, 64] = address;