pop

Pop Multiple Registers (A32)

POP<c> <registers>

Loads registers from stack (Alias for LDMIA SP!).

Pseudocode Operation

address ← SP
for each register in register_list (in ascending order)
  register ← [address]
  address ← address + 4
endfor
SP ← address

Example

POP registers

Encoding

Binary Layout

cond

31:28

100

27:25

1101

19:16

register_list

15:0

Format Load Multiple

Opcode 0x08BD0000

Extension A32 (Base)

Operands

registers
List

Other forms of pop

pop Pop (Thumb)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0xBC00	POP{<c>}{<q>} <registers>	T32	1011 \| 1 \| 10 \| P \| register_list
0x08BD0000	POP{<c>}{<q>} <registers>	A32	cond \| 100 \| 0 \| 1 \| 0 \| 1 \| 1 \| 1101 \| register_list
0xE8BD0000	POP{<c>}.W <registers>	T32	1110100 \| 01 \| 0 \| 1 \| 1 \| 1101 \| P \| M \| register_list
0x049D0004	POP{<c>}{<q>} <single_register_list>	A32	cond \| 010 \| 0 \| 1 \| 0 \| 0 \| 1 \| 1101 \| Rt \| 000000000100
0xF85D0B04	POP{<c>}{<q>} <single_register_list>	T32	111110000 \| 10 \| 1 \| 1101 \| Rt \| 1 \| 0 \| 1 \| 1 \| 00000100

Description

Loads multiple general-purpose registers from the stack, loading from consecutive memory locations starting at the address in SP, and updates SP to point just above the loaded data

pop