vld3

Vector Load Multiple (3-Element Structure)

VLD3<c>.<size> <list>, [<Rn>]{!}

Loads three-element structures (e.g., RGB) and de-interleaves them into three registers.

Details

Loads three-element interleaved structures from memory and de-interleaves them into three consecutive NEON registers. The instruction reads (3 × element_size × 8) bits from the address in Rn, distributing elements across three registers. Condition flags (N, Z, C, V) are unaffected. Execution is restricted to A32/T32 with NEON extension; post-index writeback to Rn is optional.

Pseudocode Operation

address ← Rn
for i = 0 to 7 do
  element_size_bits ← size_in_bits(size)
  Vd[i] ← [address + (i * element_size_bits / 8)]
  Vd+1[i] ← [address + (i * element_size_bits / 8) + (element_size_bits / 8)]
  Vd+2[i] ← [address + (i * element_size_bits / 8) + (2 * element_size_bits / 8)]
if (writeback) then
  Rn ← Rn + (3 * 8 * element_size_bits / 8)

Example

VLD3.size {r0-r3}, [r1]!

Encoding

Binary Layout
111101001
D
1
0
Rn
Vd
00
10
index_align
1101
 
Format NEON Load
Opcode 0xF4A0020D
Extension NEON (SIMD)

Operands

  • list
    Dest Registers
  • Rn
    First source / base general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF4A0020F VLD3{<c>}{<q>}.<size> <list>, [<Rn>] A32 111101001 | D | 1 | 0 | Rn | Vd | 00 | 10 | index_align | 1111
0xF4A0020D VLD3{<c>}{<q>}.<size> <list>, [<Rn>]! A32 111101001 | D | 1 | 0 | Rn | Vd | 00 | 10 | index_align | 1101
0xF4A00200 VLD3{<c>}{<q>}.<size> <list>, [<Rn>], <Rm> A32 111101001 | D | 1 | 0 | Rn | Vd | 00 | 10 | index_align | Rm
0xF4A0060F VLD3{<c>}{<q>}.<size> <list>, [<Rn>] A32 111101001 | D | 1 | 0 | Rn | Vd | 01 | 10 | index_align | 1111
0xF4A0060D VLD3{<c>}{<q>}.<size> <list>, [<Rn>]! A32 111101001 | D | 1 | 0 | Rn | Vd | 01 | 10 | index_align | 1101
0xF4A00600 VLD3{<c>}{<q>}.<size> <list>, [<Rn>], <Rm> A32 111101001 | D | 1 | 0 | Rn | Vd | 01 | 10 | index_align | Rm
0xF4A00A0F VLD3{<c>}{<q>}.<size> <list>, [<Rn>] A32 111101001 | D | 1 | 0 | Rn | Vd | 10 | 10 | index_align | 1111
0xF4A00A0D VLD3{<c>}{<q>}.<size> <list>, [<Rn>]! A32 111101001 | D | 1 | 0 | Rn | Vd | 10 | 10 | index_align | 1101
0xF4A00A00 VLD3{<c>}{<q>}.<size> <list>, [<Rn>], <Rm> A32 111101001 | D | 1 | 0 | Rn | Vd | 10 | 10 | index_align | Rm
0xF9A0020F VLD3{<c>}{<q>}.<size> <list>, [<Rn>] T32 111110011 | D | 1 | 0 | Rn | Vd | 00 | 10 | index_align | 1111
0xF9A0020D VLD3{<c>}{<q>}.<size> <list>, [<Rn>]! T32 111110011 | D | 1 | 0 | Rn | Vd | 00 | 10 | index_align | 1101
0xF9A00200 VLD3{<c>}{<q>}.<size> <list>, [<Rn>], <Rm> T32 111110011 | D | 1 | 0 | Rn | Vd | 00 | 10 | index_align | Rm
0xF9A0060F VLD3{<c>}{<q>}.<size> <list>, [<Rn>] T32 111110011 | D | 1 | 0 | Rn | Vd | 01 | 10 | index_align | 1111
0xF9A0060D VLD3{<c>}{<q>}.<size> <list>, [<Rn>]! T32 111110011 | D | 1 | 0 | Rn | Vd | 01 | 10 | index_align | 1101

Description

Load single 3-element structure to one lane of three registers loads one 3-element structure from memory into corresponding elements of three registers. Elements of the registers that are not loaded are unchanged. For details of the addressing mode, see Advanced SIMD addressing mode. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information, see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    address = R[n];
    Elem[D[d], index,8*ebytes] = MemU[address,ebytes];
    Elem[D[d2],index,8*ebytes] = MemU[address+ebytes,ebytes];
    Elem[D[d3],index,8*ebytes] = MemU[address+2*ebytes,ebytes];
    if wback then
        if register_index then
            R[n] = R[n] + R[m];
        else
            R[n] = R[n] + 3*ebytes;