stp

Store Pair of Registers

STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]

Stores two 32-bit registers.

Details

Stores a pair of 32-bit registers (Wt1 and Wt2) to consecutive memory locations at [Xn + (imm7 << 2)] with a signed immediate offset. This is an AArch64-only instruction commonly used for stack operations. No condition flags are affected.

Pseudocode Operation

address ← Xn + (imm7 << 2); [address] ← Wt1; [address + 4] ← Wt2

Example

STP w3, w4, [x1, #16]

Encoding

Binary Layout
00
101
0
010
0
imm7
Rt2
Rn
Rt
 
Format Load/Store Pair
Opcode 0x29000000
Extension Base

Operands

  • Wt1
    First transfer 32-bit register (load/store pair)
  • Wt2
    Second transfer 32-bit register (load/store pair)
  • Xn
    First source / base 64-bit integer register
  • imm
    Signed immediate value

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x2C800000 STP <St1>, <St2>, [<Xn|SP>], #<imm> A64 00 | 101 | 1 | 001 | 0 | imm7 | Rt2 | Rn | Rt
0x6C800000 STP <Dt1>, <Dt2>, [<Xn|SP>], #<imm> A64 01 | 101 | 1 | 001 | 0 | imm7 | Rt2 | Rn | Rt
0xAC800000 STP <Qt1>, <Qt2>, [<Xn|SP>], #<imm> A64 10 | 101 | 1 | 001 | 0 | imm7 | Rt2 | Rn | Rt
0x2D800000 STP <St1>, <St2>, [<Xn|SP>, #<imm>]! A64 00 | 101 | 1 | 011 | 0 | imm7 | Rt2 | Rn | Rt
0x6D800000 STP <Dt1>, <Dt2>, [<Xn|SP>, #<imm>]! A64 01 | 101 | 1 | 011 | 0 | imm7 | Rt2 | Rn | Rt
0xAD800000 STP <Qt1>, <Qt2>, [<Xn|SP>, #<imm>]! A64 10 | 101 | 1 | 011 | 0 | imm7 | Rt2 | Rn | Rt
0x2D000000 STP <St1>, <St2>, [<Xn|SP>{, #<imm>}] A64 00 | 101 | 1 | 010 | 0 | imm7 | Rt2 | Rn | Rt
0x6D000000 STP <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}] A64 01 | 101 | 1 | 010 | 0 | imm7 | Rt2 | Rn | Rt
0xAD000000 STP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}] A64 10 | 101 | 1 | 010 | 0 | imm7 | Rt2 | Rn | Rt
0x28800000 STP <Wt1>, <Wt2>, [<Xn|SP>], #<imm> A64 00 | 101 | 0 | 001 | 0 | imm7 | Rt2 | Rn | Rt
0xA8800000 STP <Xt1>, <Xt2>, [<Xn|SP>], #<imm> A64 10 | 101 | 0 | 001 | 0 | imm7 | Rt2 | Rn | Rt
0x29800000 STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]! A64 00 | 101 | 0 | 011 | 0 | imm7 | Rt2 | Rn | Rt
0xA9800000 STP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]! A64 10 | 101 | 0 | 011 | 0 | imm7 | Rt2 | Rn | Rt
0x29000000 STP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}] A64 00 | 101 | 0 | 010 | 0 | imm7 | Rt2 | Rn | Rt

Description

Store Pair of Registers calculates an address from a base register value and an immediate offset, and stores two 32-bit words or two 64-bit doublewords to the calculated address, from two registers. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address;
bits(64) address2;
bits(datasize) data1;
bits(datasize) data2;
constant integer dbytes = datasize DIV 8;
boolean privileged = PSTATE.EL != EL0;

AccessDescriptor accdesc = CreateAccDescGPR(MemOp_STORE, FALSE, privileged, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

if !postindex then
    address = GenerateAddress(address, offset, accdesc);

if rt_unknown && t == n then
    data1 = bits(datasize) UNKNOWN;
else
    data1 = X[t, datasize];
if rt_unknown && t2 == n then
    data2 = bits(datasize) UNKNOWN;
else
    data2 = X[t2, datasize];
if IsFeatureImplemented(FEAT_LSE2) then
    bits(2*datasize) full_data;
    if BigEndian(accdesc.acctype) then
        full_data = data1:data2;
    else
        full_data = data2:data1;
    accdesc.ispair = TRUE;
    Mem[address, 2*dbytes, accdesc] = full_data;
else
    address2 = GenerateAddress(address, dbytes, accdesc);
    Mem[address, dbytes, accdesc] = data1;
    Mem[address2, dbytes, accdesc] = data2;

if wback then
    if postindex then
        address = GenerateAddress(address, offset, accdesc);
    if n == 31 then
        SP[] = address;
    else
        X[n, 64] = address;