stp

Store Pair of Registers

STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]

Stores two 32-bit registers.

Details

The Store Pair of Registers instruction stores two 32-bit registers.

Pseudocode Operation

Memory[address] ← Wt2

Example

STP w3, w4, [x1, #16]

Encoding

Binary Layout
00101000
00
0
imm7
Rt2
Rn
Rt1
 
Format Load/Store Pair
Opcode 0x29000000
Extension Base

Operands

  • Wt1
    First transfer 32-bit register (load/store pair)
  • Wt2
    Second transfer 32-bit register (load/store pair)
  • Xn
    First source / base 64-bit integer register
  • imm
    Signed immediate value