mvn

Vector Bitwise NOT

MVN <Vd>.<T>, <Vn>.<T>

Bitwise NOT of a vector.

Details

Performs a bitwise NOT (complement) on each bit of the source vector and stores the result in the destination vector. The operation processes all elements in parallel with the same bitwise inversion applied across all bits; Q determines 64-bit (Q=0) or 128-bit (Q=1) operation. This is a NEON SIMD instruction available in AArch64 only. No condition flags are affected.

Pseudocode Operation

for i = 0 to (vector_length - 1)
  Vd.bit[i] ← NOT Vn.bit[i];

Example

MVN v0.4s.T, v1.4s.T

Encoding

Binary Layout
0
Q
1
01110
00
10000
00101
10
Rn
Rd
 
Format SIMD Two Register
Opcode 0x2E205800
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x2E205800 MVN <Vd>.<T>, <Vn>.<T> A64 0 | Q | 1 | 01110 | 00 | 10000 | 00101 | 10 | Rn | Rd
0x2A2003E0 MVN <Wd>, <Wm>{, <shift> #<amount>} A64 0 | 01 | 01010 | shift | 1 | Rm | imm6 | 11111 | Rd
0xAA2003E0 MVN <Xd>, <Xm>{, <shift> #<amount>} A64 1 | 01 | 01010 | shift | 1 | Rm | imm6 | 11111 | Rd

Description

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.