mvn

Vector Bitwise NOT

MVN <Vd>.<T>, <Vn>.<T>

Bitwise NOT of a vector.

Details

The Vector Bitwise NOT instruction bitwise NOT of a vector.

Pseudocode Operation

Vd ← NOT Vn

Example

MVN v0.4s.T, v1.4s.T

Encoding

Binary Layout
0
Q
101110
00
10000
01011
1
Rn
Rd
 
Format SIMD Two Register
Opcode 0x2E205800
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register