sturh

Store Register Halfword (Unscaled)

STURH <Wt>, [<Xn|SP>, #<simm>]

Stores a halfword using an unscaled immediate offset.

Details

Stores a halfword (16 bits) from the least-significant halfword of register Wt to memory at address Xn+simm using an unscaled immediate offset. No condition flags are affected. AArch64-only instruction that may generate an alignment fault or translation fault exception if the address is invalid or unaligned.

Pseudocode Operation

address ← Xn + SignExtend(imm9, 64)
[address, 2] ← Wt[15:0]

Example

STURH w3, [x1, #-8]

Encoding

Binary Layout
01
111
0
00
00
0
imm9
00
Rn
Rt
 
Format Load/Store
Opcode 0x78000000
Extension Base

Operands

  • Wt
    Transfer 32-bit integer register (load/store)
  • Xn
    First source / base 64-bit integer register
  • simm
    Signed immediate offset

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x78000000 STURH <Wt>, [<Xn|SP>{, #<simm>}] A64 01 | 111 | 0 | 00 | 00 | 0 | imm9 | 00 | Rn | Rt

Description

Store Register Halfword (unscaled) calculates an address from a base register value and an immediate offset, and stores a halfword to the calculated address, from a 32-bit register. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address;
bits(16) data;

boolean privileged = PSTATE.EL != EL0;
AccessDescriptor accdesc = CreateAccDescGPR(MemOp_STORE, FALSE, privileged, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

address = GenerateAddress(address, offset, accdesc);

data = X[t, 16];
Mem[address, 2, accdesc] = data;