vshl

Vector Shift Left (Immediate)

VSHL<c>.<dt> <Qd>, <Qm>, #<imm>

Shifts elements left.

Details

Shifts each element in the source register left by an immediate number of bits and stores the result in the destination register. Bits shifted out of the left end are lost, and zeros are shifted in from the right. The shift amount is applied uniformly to all elements and is encoded in the imm6 field, with the interpretation dependent on element size (sz). Condition flags (N, Z, C, V) are not affected. Executes in A32/T32 with NEON extension.

Pseudocode Operation

shift_amount ← DecodeImmShift(imm6, sz)  // Decodes imm6 based on element size
for i = 0 to 127 by element_size:
  element ← Qm[i+element_size-1:i]
  Qd[i+element_size-1:i] ← element << shift_amount

Example

VSHL.dt q0, q2, #16

Encoding

Binary Layout
1111001
0
1
D
imm6
Vd
0101
L
0
M
1
Vm
 
Format NEON Shift
Opcode 0xF2800510
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register
  • imm
    Signed immediate value

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2800510 VSHL{<c>}{<q>}.I<size> {<Dd>,} <Dm>, #<imm> A32 1111001 | 0 | 1 | D | imm6 | Vd | 0101 | L | 0 | M | 1 | Vm
0xF2800550 VSHL{<c>}{<q>}.I<size> {<Qd>,} <Qm>, #<imm> A32 1111001 | 0 | 1 | D | imm6 | Vd | 0101 | L | 1 | M | 1 | Vm
0xEF800510 VSHL{<c>}{<q>}.I<size> {<Dd>,} <Dm>, #<imm> T32 111 | 0 | 11111 | D | imm6 | Vd | 0101 | L | 0 | M | 1 | Vm
0xEF800550 VSHL{<c>}{<q>}.I<size> {<Qd>,} <Qm>, #<imm> T32 111 | 0 | 11111 | D | imm6 | Vd | 0101 | L | 1 | M | 1 | Vm
0xF2000400 VSHL{<c>}{<q>}.<dt> {<Dd>,} <Dm>, <Dn> A32 1111001 | U | 0 | D | size | Vn | Vd | 0100 | N | 0 | M | 0 | Vm
0xF2000440 VSHL{<c>}{<q>}.<dt> {<Qd>,} <Qm>, <Qn> A32 1111001 | U | 0 | D | size | Vn | Vd | 0100 | N | 1 | M | 0 | Vm
0xEF000400 VSHL{<c>}{<q>}.<dt> {<Dd>,} <Dm>, <Dn> T32 111 | U | 11110 | D | size | Vn | Vd | 0100 | N | 0 | M | 0 | Vm
0xEF000440 VSHL{<c>}{<q>}.<dt> {<Qd>,} <Qm>, <Qn> T32 111 | U | 11110 | D | size | Vn | Vd | 0100 | N | 1 | M | 0 | Vm

Description

Vector Shift Left (immediate) takes each element in a vector of integers, left shifts them by an immediate value, and places the results in the destination vector. Bits shifted out of the left of each element are lost. The elements must all be the same size, and can be 8-bit, 16-bit, 32-bit, or 64-bit integers. There is no distinction between signed and unsigned integers. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        for e = 0 to elements-1
            Elem[D[d+r],e,esize] = LSL(Elem[D[m+r],e,esize], shift_amount);