sub

Subtract (Shifted Register)

SUB <Wd>, <Wn>, <Wm> {, <shift> #<amount>}

Subtracts shifted register from register.

Details

Subtracts the value in the second source register (optionally shifted) from the first source register and writes the result to the destination register. The shift can be LSL, LSR, ASR, or ROR by an amount specified in the immediate field. The condition flags (N, Z, C, V) are not affected. This instruction executes in AArch64 state and requires no special privileges.

Pseudocode Operation

shift_amount ← imm6; shifted_Wm ← ApplyShift(Wm, shift_type, shift_amount); Wd ← Wn - shifted_Wm

Example

SUB w0, w1, w2

Encoding

Binary Layout
0
1
0
01011
shift
0
Rm
imm6
Rn
Rd
 
Format Data Processing
Opcode 0x4B000000
Extension Base

Operands

  • Wd
    Destination 32-bit integer register
  • Wn
    First source / base 32-bit integer register
  • Wm
    Second source / offset 32-bit integer register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x4B200000 SUB <Wd|WSP>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}} A64 0 | 1 | 0 | 01011 | 00 | 1 | Rm | option | imm3 | Rn | Rd
0xCB200000 SUB <Xd|SP>, <Xn|SP>, <R><m>{, <extend> {#<amount>}} A64 1 | 1 | 0 | 01011 | 00 | 1 | Rm | option | imm3 | Rn | Rd
0x51000000 SUB <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>} A64 0 | 1 | 0 | 100010 | sh | imm12 | Rn | Rd
0xD1000000 SUB <Xd|SP>, <Xn|SP>, #<imm>{, <shift>} A64 1 | 1 | 0 | 100010 | sh | imm12 | Rn | Rd
0x4B000000 SUB <Wd>, <Wn>, <Wm>{, <shift> #<amount>} A64 0 | 1 | 0 | 01011 | shift | 0 | Rm | imm6 | Rn | Rd
0xCB000000 SUB <Xd>, <Xn>, <Xm>{, <shift> #<amount>} A64 1 | 1 | 0 | 01011 | shift | 0 | Rm | imm6 | Rn | Rd
0x7EE08400 SUB D<d>, D<n>, D<m> A64 01 | 1 | 11110 | 11 | 1 | Rm | 10000 | 1 | Rn | Rd
0x2E208400 SUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 1 | 01110 | size | 1 | Rm | 10000 | 1 | Rn | Rd
0x04010000 SUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 00000100 | size | 000 | 00 | 1 | 000 | Pg | Zm | Zdn
0x2521C000 SUB <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>} A64 00100101 | size | 100 | 00 | 1 | 11 | sh | imm8 | Zdn
0x04200400 SUB <Zd>.<T>, <Zn>.<T>, <Zm>.<T> A64 00000100 | size | 1 | Zm | 000 | 00 | 1 | Zn | Zd
0xC1A01C18 SUB ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zm1>.<T>-<Zm2>.<T> } A64 110000011 | sz | 1000000 | Rv | 111 | Zm | 01 | 1 | off3
0xC1A11C18 SUB ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zm1>.<T>-<Zm4>.<T> } A64 110000011 | sz | 1000010 | Rv | 111 | Zm | 001 | 1 | off3
0xC1201818 SUB ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zn1>.<T>-<Zn2>.<T> }, <Zm>.<T> A64 110000010 | sz | 10 | Zm | 0 | Rv | 110 | Zn | 1 | 1 | off3

Description

Subtract (shifted register) subtracts an optionally-shifted register value from a register value, and writes the result to the destination register.

Operation

bits(datasize) result;
bits(datasize) operand1 = X[n, datasize];
bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount, datasize);

operand2 = NOT(operand2);
(result, -) = AddWithCarry(operand1, operand2, '1');

X[d, datasize] = result;