ldarh

Load-Acquire Register Halfword

LDARH <Wt>, [<Xn|SP>]

Loads a halfword with Acquire semantics.

Pseudocode Operation

Wt ← ZeroExtend(Mem16[Xn], 16)
# Acquire semantics: subsequent memory operations appear after this load

Example

LDARH w3, [x1]

Encoding

Binary Layout

01

31:30

0010001

29:23

1

22

0

21

11111

20:16

1

15

11111

14:10

Rn

9:5

Rt

4:0

 

Format Load/Store

Opcode 0x48DFFC00

Extension Base (Atomic)

Operands

• Wt
  Transfer 32-bit integer register (load/store)
• Xn
  First source / base 64-bit integer register

Related

More in Base (Atomic)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x48DFFC00	LDARH <Wt>, [<Xn|SP>{, #0}]		A64		01 | 0010001 | 1 | 0 | 11111 | 1 | 11111 | Rn | Rt

Description

Load-Acquire Register Halfword derives an address from a base register value, loads a halfword from memory, zero-extends it, and writes it to a register. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address;
bits(16) data;

AccessDescriptor accdesc;
accdesc = CreateAccDescAcqRel(MemOp_LOAD, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

data = Mem[address, 2, accdesc];
X[t, 32] = ZeroExtend(data, 32);