ldarh

Load-Acquire Register Halfword

LDARH <Wt>, [<Xn|SP>]

Loads a halfword with Acquire semantics.

Details

Load-Acquire Register Halfword loads a 16-bit halfword from memory with Acquire semantics, establishing a one-way barrier that prevents subsequent memory operations from being observed before the load completes. The instruction is AArch64-only, does not modify condition flags, and the loaded halfword is zero-extended to 32 bits in the destination register.

Pseudocode Operation

Wt ← ZeroExtend(Mem16[Xn], 16)
# Acquire semantics: subsequent memory operations appear after this load

Example

LDARH w3, [x1]

Encoding

Binary Layout
01
0010001
1
0
11111
1
11111
Rn
Rt
 
Format Load/Store
Opcode 0x48DFFC00
Extension Base (Atomic)

Operands

  • Wt
    Transfer 32-bit integer register (load/store)
  • Xn
    First source / base 64-bit integer register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x48DFFC00 LDARH <Wt>, [<Xn|SP>{, #0}] A64 01 | 0010001 | 1 | 0 | 11111 | 1 | 11111 | Rn | Rt

Description

Load-Acquire Register Halfword derives an address from a base register value, loads a halfword from memory, zero-extends it, and writes it to a register. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address;
bits(16) data;

AccessDescriptor accdesc;
accdesc = CreateAccDescAcqRel(MemOp_LOAD, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

data = Mem[address, 2, accdesc];
X[t, 32] = ZeroExtend(data, 32);