bfadd

BFloat16 Add

BFADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

Adds BFloat16 elements.

Details

Adds BFloat16 (16-bit) elements from two SVE registers under predicate control and stores the result in the destination register. Floating-point exceptions may be generated; condition flags are unaffected. Requires FEAT_SVE_B16B16; AArch64 only.

Pseudocode Operation

for i = 0 to VL/16 - 1
  if Pg[i]
    Zdn[i] ← FP_Add(Zdn[i], Zm[i], RMode_TONEAREST)
  else
    Zdn[i] ← Zdn[i]

Example

BFADD z0.s.T, p0/m/M, z0.s.T, z2.s.T

Encoding

Binary Layout
01100101
0
0
0
Zm
000
00
0
Zn
Zd
 
Format SVE BFloat16
Opcode 0x65000000
Extension FEAT_SVE_B16B16

Operands

  • Zdn
    Dest/Src
  • Pg
    Mask
  • Zm
    Second source scalable vector register (SVE)

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x65008000 BFADD <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H A64 01100101 | 0 | 0 | 00 | 000 | 0 | 100 | Pg | Zm | Zdn
0x65000000 BFADD <Zd>.H, <Zn>.H, <Zm>.H A64 01100101 | 0 | 0 | 0 | Zm | 000 | 00 | 0 | Zn | Zd
0xC1E41C00 BFADD ZA.H[<Wv>, <offs>{, VGx2}], { <Zm1>.H-<Zm2>.H } A64 110000011 | 1 | 1001000 | Rv | 111 | Zm | 00 | 0 | off3
0xC1E51C00 BFADD ZA.H[<Wv>, <offs>{, VGx4}], { <Zm1>.H-<Zm4>.H } A64 110000011 | 1 | 1001010 | Rv | 111 | Zm | 000 | 0 | off3

Description

Add all BFloat16 elements of the second source vector to corresponding elements of the first source vector and place the results in the corresponding elements of the destination vector. This instruction follows SVE2.1 non-widening BFloat16 numerical behaviors. This instruction is unpredicated. ID_AA64ZFR0_EL1.B16B16 indicates whether this instruction is implemented.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer elements = VL DIV 16;
bits(VL) operand1 = Z[n, VL];
bits(VL) operand2 = Z[m, VL];
bits(VL) result;

for e = 0 to elements-1
    bits(16) element1 = Elem[operand1, e, 16];
    bits(16) element2 = Elem[operand2, e, 16];
    Elem[result, e, 16] = BFAdd(element1, element2, FPCR);

Z[d, VL] = result;