at

Address Translate (Stage 1 Current)

AT S1E1R, <Xt>

Performs stage 1 address translation for current EL.

Pseudocode Operation

address ← Xt
translation_result ← TranslateAddress(address, S1E1R, current_EL)
PAR_EL1 ← translation_result

Example

AT S1E1R, x3

Encoding

Binary Layout

1101010100

31:22

0

21

01

20:19

op1

18:16

0111

15:12

CRm

11:8

op2

7:5

Rt

4:0

 

Format System

Opcode 0xD5087800

Extension Base (System)

Operands

• Xt
  Virt Addr

Related

Other forms of at

• at Address Translate (Stage 1 Write)
• at Address Translate

More in Base (System)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xD5087800	AT <at_op>, <Xt>		A64		1101010100 | 0 | 01 | op1 | 0111 | CRm | op2 | Rt

Description

Address Translate. For more information, see op0==0b01, cache maintenance, TLB maintenance, and address translation instructions.