madd

Multiply-Add (64-bit)

MADD <Xd>, <Xn>, <Xm>, <Xa>

Calculates (Xa + (Xn * Xm)).

Details

Multiply-Add: multiplies Xn by Xm and adds the result to Xa, storing the 64-bit result in Xd. Does not affect condition flags. AArch64-only instruction with no privilege restrictions.

Pseudocode Operation

Xd ← Xa + (Xn × Xm)

Example

MADD x0, x1, x2, x5

Encoding

Binary Layout
1
00
11011
000
Rm
0
Ra
Rn
Rd
 
Format Data Processing
Opcode 0x9B000000
Extension Base

Operands

  • Xd
    Destination 64-bit integer register
  • Xn
    First source / base 64-bit integer register
  • Xm
    Second source / offset 64-bit integer register
  • Xa
    Addend

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x1B000000 MADD <Wd>, <Wn>, <Wm>, <Wa> A64 0 | 00 | 11011 | 000 | Rm | 0 | Ra | Rn | Rd
0x9B000000 MADD <Xd>, <Xn>, <Xm>, <Xa> A64 1 | 00 | 11011 | 000 | Rm | 0 | Ra | Rn | Rd

Description

Multiply-Add multiplies two register values, adds a third register value, and writes the result to the destination register.

Operation

bits(destsize) operand1 = X[n, destsize];
bits(destsize) operand2 = X[m, destsize];
bits(destsize) operand3 = X[a, destsize];

integer result;

result = UInt(operand3) + (UInt(operand1) * UInt(operand2));

X[d, destsize] = result<destsize-1:0>;