fcvtps

Floating-Point Convert to Signed Integer (Plus Infinity)

FCVTPS <Wd|Xd>, <Hn|Sn|Dn>

Converts float to signed integer, rounding towards plus infinity (Ceil).

Details

Converts a floating-point value to a signed integer, rounding towards plus infinity (ceiling). The source is read from a half-precision (H), single-precision (S), or double-precision (D) FP register, and the result is written to a 32-bit (W) or 64-bit (X) general-purpose register. NZCV flags are not affected by this instruction. This is an AArch64-only instruction that executes at any privilege level.

Pseudocode Operation

if source_is_nan then
  result ← 0
else
  result ← round_to_plus_infinity(FP_to_signed_integer(Vn))
Rd ← result

Example

FCVTPS Wd, Dn

Encoding

Binary Layout
0
0
0
11110
00
1
01
000
000000
Rn
Rd
 
Format FP Conversion
Opcode 0x1E280000
Extension Floating Point

Operands

  • Rd
    Int Dest
  • Vn
    Float Src

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x5EF9A800 FCVTPS <Hd>, <Hn> A64 01 | 0 | 11110 | 1 | 1111001101 | 0 | 10 | Rn | Rd
0x5EA1A800 FCVTPS <V><d>, <V><n> A64 01 | 0 | 11110 | 1 | sz | 100001101 | 0 | 10 | Rn | Rd
0x0EF9A800 FCVTPS <Vd>.<T>, <Vn>.<T> A64 0 | Q | 0 | 01110 | 1 | 1111001101 | 0 | 10 | Rn | Rd
0x0EA1A800 FCVTPS <Vd>.<T>, <Vn>.<T> A64 0 | Q | 0 | 01110 | 1 | sz | 100001101 | 0 | 10 | Rn | Rd
0x1EE80000 FCVTPS <Wd>, <Hn> A64 0 | 0 | 0 | 11110 | 11 | 1 | 01 | 000 | 000000 | Rn | Rd
0x9EE80000 FCVTPS <Xd>, <Hn> A64 1 | 0 | 0 | 11110 | 11 | 1 | 01 | 000 | 000000 | Rn | Rd
0x1E280000 FCVTPS <Wd>, <Sn> A64 0 | 0 | 0 | 11110 | 00 | 1 | 01 | 000 | 000000 | Rn | Rd
0x9E280000 FCVTPS <Xd>, <Sn> A64 1 | 0 | 0 | 11110 | 00 | 1 | 01 | 000 | 000000 | Rn | Rd
0x1E680000 FCVTPS <Wd>, <Dn> A64 0 | 0 | 0 | 11110 | 01 | 1 | 01 | 000 | 000000 | Rn | Rd
0x9E680000 FCVTPS <Xd>, <Dn> A64 1 | 0 | 0 | 11110 | 01 | 1 | 01 | 000 | 000000 | Rn | Rd

Description

Floating-point Convert to Signed integer, rounding toward Plus infinity (scalar). This instruction converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit signed integer using the Round towards Plus Infinity rounding mode, and writes the result to the general-purpose destination register. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();

bits(decode_fltsize) fltval;
bits(intsize) intval;

fltval = V[n, decode_fltsize];
intval = FPToFixed(fltval, 0, FALSE, FPCR, rounding, intsize);
X[d, intsize] = intval;