sdot

Signed Dot Product (NEON)

SDOT <Vd>.4S, <Vn>.16B, <Vm>.16B

Dot product of signed integers (AArch64 NEON).

Pseudocode Operation

for i = 0 to 3 do
  sum ← 0
  for j = 0 to 3 do
    sum ← sum + SignExtend(Vn.B[4*i + j], 32) × SignExtend(Vm.B[4*i + j], 32)
  endfor
  Vd.S[i] ← Vd.S[i] + sum
endfor

Example

SDOT v0.4s.4S, v1.4s.16B, v2.4s.16B

Encoding

Binary Layout
0
31
Q
30
0
29
01110
28:24
size
23:22
0
21
Rm
20:16
1
15
0010
14:11
1
10
Rn
9:5
Rd
4:0
 
Format NEON DotProd
Opcode 0x0E009400
Extension FEAT_DotProd

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register

Related

Other forms of sdot

  • sdot SVE Signed Dot Product
  • sdot Signed Dot Product (A32)
  • sdot Signed Dot Product (Multi-vector)

More in FEAT_DotProd

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0F00E000 SDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.4B[<index>] A64 0 | Q | 0 | 01111 | size | L | M | Rm | 1110 | H | 0 | Rn | Rd
0x0E009400 SDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> A64 0 | Q | 0 | 01110 | size | 0 | Rm | 1 | 0010 | 1 | Rn | Rd
0x4400C800 SDOT <Zda>.S, <Zn>.H, <Zm>.H A64 01000100000 | Zm | 11001 | 0 | Zn | Zda
0x4480C800 SDOT <Zda>.S, <Zn>.H, <Zm>.H[<imm>] A64 01000100100 | i2 | Zm | 11001 | 0 | Zn | Zda
0x44000000 SDOT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> A64 01000100 | size | 0 | Zm | 00000 | 0 | Zn | Zda
0x44A00000 SDOT <Zda>.S, <Zn>.B, <Zm>.B[<imm>] A64 01000100 | 1 | 0 | 1 | i2 | Zm | 00000 | 0 | Zn | Zda
0x44E00000 SDOT <Zda>.D, <Zn>.H, <Zm>.H[<imm>] A64 01000100 | 1 | 1 | 1 | i1 | Zm | 00000 | 0 | Zn | Zda
0xC1501000 SDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] A64 110000010101 | Zm | 0 | Rv | 1 | i2 | Zn | 0 | 0 | 0 | off3
0xC1509000 SDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] A64 110000010101 | Zm | 1 | Rv | 1 | i2 | Zn | 0 | 0 | 0 | 0 | off3
0xC1601408 SDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H A64 11 | 0000010110 | Zm | 0 | Rv | 101 | Zn | 0 | 1 | off3
0xC1701408 SDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H A64 11 | 0000010111 | Zm | 0 | Rv | 101 | Zn | 0 | 1 | off3
0xC1E01408 SDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } A64 11 | 000001111 | Zm | 00 | Rv | 101 | Zn | 0 | 0 | 1 | off3
0xC1E11408 SDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H } A64 11 | 000001111 | Zm | 010 | Rv | 101 | Zn | 00 | 0 | 1 | off3
0xC1501020 SDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>] A64 110000010101 | Zm | 0 | Rv | 1 | i2 | Zn | 1 | 0 | 0 | off3

Description

Dot Product signed arithmetic (vector). This instruction performs the dot product of the four signed 8-bit elements in each 32-bit element of the first source register with the four signed 8-bit elements of the corresponding 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. In Armv8.2 and Armv8.3, this is an OPTIONAL instruction. From Armv8.4 it is mandatory for all implementations to support it.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;

result = V[d, datasize];
for e = 0 to elements-1
    integer res = 0;
    integer element1, element2;
    for i = 0 to 3
        if signed then
            element1 = SInt(Elem[operand1, 4*e+i, esize DIV 4]);
            element2 = SInt(Elem[operand2, 4*e+i, esize DIV 4]);
        else
            element1 = UInt(Elem[operand1, 4*e+i, esize DIV 4]);
            element2 = UInt(Elem[operand2, 4*e+i, esize DIV 4]);
        res = res + element1 * element2;
    Elem[result, e, esize] = Elem[result, e, esize] + res;
V[d, datasize] = result;