mul

Vector Multiply (Integer)

MUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Multiplies corresponding elements in two vectors.

Details

Multiplies corresponding integer elements in two NEON vectors and writes the results to the destination vector. Operates element-wise on 8-bit, 16-bit, or 32-bit elements; the result is the lower bits of the product (wrapping multiplication). Condition flags (N, Z, C, V) are not affected.

Pseudocode Operation

for i = 0 to elements_in_vector - 1
  Vd[i] ← (Vn[i] × Vm[i]) mod 2^element_width

Example

MUL v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout
0
Q
0
01110
size
1
Rm
10011
1
Rn
Rd
 
Format SIMD Three Register
Opcode 0x0E209C00
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0F008000 MUL <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>] A64 0 | Q | 0 | 01111 | size | L | M | Rm | 1000 | H | 0 | Rn | Rd
0x0E209C00 MUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 0 | 01110 | size | 1 | Rm | 10011 | 1 | Rn | Rd
0x1B007C00 MUL <Wd>, <Wn>, <Wm> A64 0 | 00 | 11011 | 000 | Rm | 0 | 11111 | Rn | Rd
0x9B007C00 MUL <Xd>, <Xn>, <Xm> A64 1 | 00 | 11011 | 000 | Rm | 0 | 11111 | Rn | Rd
0x04100000 MUL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 00000100 | size | 0100 | 0 | 0 | 000 | Pg | Zm | Zdn
0x2530C000 MUL <Zdn>.<T>, <Zdn>.<T>, #<imm> A64 00100101 | size | 110 | 00 | 0 | 11 | 0 | imm8 | Zdn
0x04206000 MUL <Zd>.<T>, <Zn>.<T>, <Zm>.<T> A64 00000100 | size | 1 | Zm | 0110 | 0 | 0 | Zn | Zd
0x4420F800 MUL <Zd>.H, <Zn>.H, <Zm>.H[<imm>] A64 01000100 | 0 | i3h | 1 | i3l | Zm | 111110 | Zn | Zd
0x44A0F800 MUL <Zd>.S, <Zn>.S, <Zm>.S[<imm>] A64 01000100 | 1 | 0 | 1 | i2 | Zm | 111110 | Zn | Zd
0x44E0F800 MUL <Zd>.D, <Zn>.D, <Zm>.D[<imm>] A64 01000100 | 1 | 1 | 1 | i1 | Zm | 111110 | Zn | Zd

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if poly then
        product = PolynomialMult(element1, element2)<esize-1:0>;
    else
        product = (UInt(element1)*UInt(element2))<esize-1:0>;
    Elem[result, e, esize] = product;

V[d, datasize] = result;