sxth

Signed Extend Halfword (A32)

SXTH<c> <Rd>, <Rm> {, <rotation>}

Sign-extends the low halfword (16-bits) to 32-bits.

Pseudocode Operation

rotated ← ROR(Rm, rotation)
Rd ← SignExtend(rotated[15:0], 32)

Example

SXTH r0, r2

Encoding

Binary Layout

cond

31:28

01101

27:23

0

22

11

21:20

1111

19:16

Rd

15:12

rotate

11:10

0

9

0

8

0111

7:4

Rm

3:0

 

Format Data Proc

Opcode 0x06BF0070

Extension A32 (Base)

Operands

• Rd
  Destination general-purpose register
• Rm
  Second source / offset general-purpose register

Related

Other forms of sxth

• sxth Signed Extend Halfword (Thumb)

More in A32 (Base)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x06BF0070	SXTH{<c>}{<q>} {<Rd>,} <Rm> {, ROR #<amount>}		A32		cond | 01101 | 0 | 11 | 1111 | Rd | rotate | 0 | 0 | 0111 | Rm
0xB200	SXTH{<c>}{<q>} {<Rd>,} <Rm>		T32		10110010 | 0 | 0 | Rm | Rd
0xFA0FF080	SXTH{<c>}.W {<Rd>,} <Rm>		T32		111110100 | 00 | 0 | 1111 | 1111 | Rd | 1 | 0 | rotate | Rm

Description

Signed Extend Halfword extracts a 16-bit value from a register, sign-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    rotated = ROR(R[m], rotation);
    R[d] = SignExtend(rotated<15:0>, 32);