sxth

Signed Extend Halfword (A32)

SXTH<c> <Rd>, <Rm> {, <rotation>}

Sign-extends the low halfword (16-bits) to 32-bits.

Details

Sign-extends the low halfword of Rm into the full 32-bit word in Rd, with optional pre-rotation of Rm by 0, 8, 16, or 24 bits. This is an A32 instruction that does not affect any condition flags. The rotation is applied before the sign extension.

Pseudocode Operation

rotated ← ROR(Rm, rotation)
Rd ← SignExtend(rotated[15:0], 32)

Example

SXTH r0, r2

Encoding

Binary Layout
cond
01101
0
11
1111
Rd
rotate
0
0
0111
Rm
 
Format Data Proc
Opcode 0x06BF0070
Extension A32 (Base)

Operands

  • Rd
    Destination general-purpose register
  • Rm
    Second source / offset general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x06BF0070 SXTH{<c>}{<q>} {<Rd>,} <Rm> {, ROR #<amount>} A32 cond | 01101 | 0 | 11 | 1111 | Rd | rotate | 0 | 0 | 0111 | Rm
0xB200 SXTH{<c>}{<q>} {<Rd>,} <Rm> T32 10110010 | 0 | 0 | Rm | Rd
0xFA0FF080 SXTH{<c>}.W {<Rd>,} <Rm> T32 111110100 | 00 | 0 | 1111 | 1111 | Rd | 1 | 0 | rotate | Rm

Description

Signed Extend Halfword extracts a 16-bit value from a register, sign-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    rotated = ROR(R[m], rotation);
    R[d] = SignExtend(rotated<15:0>, 32);