umaal

Unsigned Multiply Accumulate Accumulate Long

UMAAL<c> <RdLo>, <RdHi>, <Rn>, <Rm>

Calculates (Rn * Rm) + RdLo + RdHi -> 64-bit result.

Details

Unsigned Multiply Accumulate Accumulate Long multiplies Rn by Rm, adds both RdLo and RdHi to the product, and writes the 64-bit result back to RdLo:RdHi. All operands are treated as unsigned 32-bit values. Condition flags are not affected; RdLo and RdHi must be different registers. This instruction is available in A32/T32 and requires the DSP extension on some implementations.

Pseudocode Operation

temp ← (Rn * Rm) + RdLo + RdHi
RdLo ← temp[31:0]
RdHi ← temp[63:32]

Example

UMAAL r1, r0, r1, r2

Encoding

Binary Layout
cond
0000
010
0
RdHi
RdLo
Rm
1001
Rn
 
Format Multiply
Opcode 0x00400090
Extension A32 (DSP)

Operands

  • RdLo
    Dest Lo/Acc
  • RdHi
    Dest Hi/Acc
  • Rn
    First source / base general-purpose register
  • Rm
    Second source / offset general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x00400090 UMAAL{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm> A32 cond | 0000 | 010 | 0 | RdHi | RdLo | Rm | 1001 | Rn
0xFBE00060 UMAAL{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm> T32 111110111 | 110 | Rn | RdLo | RdHi | 0110 | Rm

Description

Unsigned Multiply Accumulate Accumulate Long multiplies two unsigned 32-bit values to produce a 64-bit value, adds two unsigned 32-bit values, and writes the 64-bit result to two registers.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    result = UInt(R[n]) * UInt(R[m]) + UInt(R[dHi]) + UInt(R[dLo]);
    R[dHi] = result<63:32>;
    R[dLo] = result<31:0>;