fadd

Floating-point Add (Single)

FADD <Sd>, <Sn>, <Sm>

Adds two single-precision floating-point registers.

Details

The Floating-point Add instruction adds two single-precision floating-point registers.

Pseudocode Operation

Sd ← Sn + Sm
// Flags affected: N, Z, C, V

Example

FADD s0, s1, s2

Encoding

Binary Layout
00011110
001
Rm
001010
Rn
Rd
 
Format Float Data Proc
Opcode 0x1E202800
Extension F.P.

Operands

  • Sd
    Dest (32-bit)
  • Sn
    First source 32-bit floating-point register
  • Sm
    Second source 32-bit floating-point register