ldrsb

Load Register Signed Byte (Immediate)

LDRSB <Wt>, [<Xn|SP>, #<pimm>]

Loads a byte and sign-extends it to 32-bits.

Details

Loads a signed byte from memory using immediate offset and sign-extends it to 32 bits. No condition flags are affected. This is an AArch64 Base instruction that executes in all privilege levels.

Pseudocode Operation

address ← Xn + (pimm << 0);
Wt ← SignExtend(Mem[address, 1], 32);

Example

LDRSB w3, [x1, #16]

Encoding

Binary Layout
00
111
0
01
11
imm12
Rn
Rt
 
Format Load/Store
Opcode 0x39C00000
Extension Base

Operands

  • Wt
    Transfer 32-bit integer register (load/store)
  • Xn
    First source / base 64-bit integer register
  • pimm
    Positive immediate offset

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x38C00400 LDRSB <Wt>, [<Xn|SP>], #<simm> A64 00 | 111 | 0 | 00 | 11 | 0 | imm9 | 01 | Rn | Rt
0x38800400 LDRSB <Xt>, [<Xn|SP>], #<simm> A64 00 | 111 | 0 | 00 | 10 | 0 | imm9 | 01 | Rn | Rt
0x38C00C00 LDRSB <Wt>, [<Xn|SP>, #<simm>]! A64 00 | 111 | 0 | 00 | 11 | 0 | imm9 | 11 | Rn | Rt
0x38800C00 LDRSB <Xt>, [<Xn|SP>, #<simm>]! A64 00 | 111 | 0 | 00 | 10 | 0 | imm9 | 11 | Rn | Rt
0x39C00000 LDRSB <Wt>, [<Xn|SP>{, #<pimm>}] A64 00 | 111 | 0 | 01 | 11 | imm12 | Rn | Rt
0x39800000 LDRSB <Xt>, [<Xn|SP>{, #<pimm>}] A64 00 | 111 | 0 | 01 | 10 | imm12 | Rn | Rt
0x38E00800 LDRSB <Wt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}] A64 00 | 111 | 0 | 00 | 11 | 1 | Rm | option | S | 10 | Rn | Rt
0x38E06800 LDRSB <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}] A64 00 | 111 | 0 | 00 | 11 | 1 | Rm | 011 | S | 10 | Rn | Rt
0x38A00800 LDRSB <Xt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}] A64 00 | 111 | 0 | 00 | 10 | 1 | Rm | option | S | 10 | Rn | Rt
0x38A06800 LDRSB <Xt>, [<Xn|SP>, <Xm>{, LSL <amount>}] A64 00 | 111 | 0 | 00 | 10 | 1 | Rm | 011 | S | 10 | Rn | Rt

Description

Load Register Signed Byte (immediate) loads a byte from memory, sign-extends it to either 32 bits or 64 bits, and writes the result to a register. The address that is used for the load is calculated from a base register and an immediate offset. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address;
bits(8) data;

boolean privileged = PSTATE.EL != EL0;
AccessDescriptor accdesc = CreateAccDescGPR(memop, FALSE, privileged, tagchecked);

if n == 31 then
    if memop != MemOp_PREFETCH then CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

if !postindex then
    address = GenerateAddress(address, offset, accdesc);

case memop of
    when MemOp_STORE
        if rt_unknown then
            data = bits(8) UNKNOWN;
        else
            data = X[t, 8];
        Mem[address, 1, accdesc] = data;

    when MemOp_LOAD
        data = Mem[address, 1, accdesc];
        if signed then
            X[t, regsize] = SignExtend(data, regsize);
        else
            X[t, regsize] = ZeroExtend(data, regsize);

    when MemOp_PREFETCH
        Prefetch(address, t<4:0>);

if wback then
    if wb_unknown then
        address = bits(64) UNKNOWN;
    elsif postindex then
        address = GenerateAddress(address, offset, accdesc);
    if n == 31 then
        SP[] = address;
    else
        X[n, 64] = address;