trn1

Vector Transpose 1

TRN1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Transposes elements (Lower).

Details

Transposes elements by interleaving lower halves of Vn and Vm in a transposition pattern, selecting alternate elements from Vn first. This is a pure permutation with no flag updates. Execution is restricted to AArch64 with NEON support (ARMv8.0+).

Pseudocode Operation

bits(128) result;
for e = 0 to (esize/16)-1
  result[e*16 +: 8] ← Vn[e*16 +: 8];
  result[e*16 + 8 +: 8] ← Vm[e*16 +: 8];
if Q == 0 then
  Vd ← result[0 +: 64];
else
  Vd ← result;

Example

TRN1 v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout
0
Q
001110
size
0
Rm
0
0
1010
Rn
Rd
 
Format SIMD Permute
Opcode 0x0E002800
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0E002800 TRN1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 001110 | size | 0 | Rm | 0 | 0 | 1010 | Rn | Rd
0x05205000 TRN1 <Pd>.<T>, <Pn>.<T>, <Pm>.<T> A64 00000101 | size | 10 | Pm | 010 | 1 | 0 | 0 | 0 | Pn | 0 | Pd
0x05207000 TRN1 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> A64 00000101 | size | 1 | Zm | 011 | 10 | 0 | Zn | Zd
0x05A01800 TRN1 <Zd>.Q, <Zn>.Q, <Zm>.Q A64 00000101101 | Zm | 000 | 1 | 1 | 0 | Zn | Zd

Description

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;

for p = 0 to pairs-1
    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];

V[d, datasize] = result;