mrs

Move Status Register to Register

MRS<c> <Rd>, <spec_reg>

Reads CPSR or SPSR.

Pseudocode Operation

if R == 0 then
  Rd ← CPSR
else
  Rd ← SPSR

Example

MRS r0, nzcv

Encoding

Binary Layout

cond

31:28

00010

27:23

1111

19:16

15:12

0000

7:4

0000

3:0

Format System

Opcode 0x010F0000

Extension A32 (System)

Operands

Rd
Destination general-purpose register
spec_reg
CPSR/SPSR

Other forms of mrs

mrs Move System Register
mrs Move from Special Register (Banked)
mrs Move Special Register to Register (Thumb)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x010F0000	MRS{<c>}{<q>} <Rd>, <spec_reg>	A32	cond \| 00010 \| R \| 0 \| 0 \| 1111 \| Rd \| 0 \| 0 \| 0 \| 0 \| 0000 \| 0000
0xF3EF8000	MRS{<c>}{<q>} <Rd>, <spec_reg>	T32	11110011111 \| R \| 1 \| 1 \| 1 \| 1 \| 10 \| 0 \| 0 \| Rd \| 0 \| 0 \| 0 \| 0 \| 0 \| 0 \| 0 \| 0
0x01000200	MRS{<c>}{<q>} <Rd>, <banked_reg>	A32	cond \| 00010 \| R \| 0 \| 0 \| M1 \| Rd \| 0 \| 0 \| 1 \| M \| 0000 \| 0000
0xF3E08020	MRS{<c>}{<q>} <Rd>, <banked_reg>	T32	11110011111 \| R \| M1 \| 10 \| 0 \| 0 \| Rd \| 0 \| 0 \| 1 \| M \| 0 \| 0 \| 0 \| 0

Description

Move Special register to general-purpose register moves the value of the APSR, CPSR, or SPSR_<current_mode> into a general-purpose register. Arm recommends the APSR form when only the N, Z, C, V, Q, and GE[3:0] bits are being written. For more information, see APSR. An MRS that accesses the SPSRs is unpredictable if executed in User mode or System mode. An MRS that is executed in User mode and accesses the CPSR returns an unknown value for the CPSR.{E, A, I, F, M} fields.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    if read_spsr then
        if PSTATE.M IN {M32_User,M32_System} then
            UNPREDICTABLE;
        else
            R[d] = SPSR[];
    else
        // CPSR has same bit assignments as SPSR, but with the IT, J, SS, IL, and T bits masked out.
        bits(32) mask = '11111000 11101111 00000011 11011111';
        psr_val = GetPSRFromPSTATE(AArch32_NonDebugState, 32) AND mask;
        if PSTATE.EL == EL0 then
            // If accessed from User mode return UNKNOWN values for E, A, I, F bits, bits<9:6>,
            // and for the M field, bits<4:0>
            psr_val<22> = bits(1) UNKNOWN;
            psr_val<9:6> = bits(4) UNKNOWN;
            psr_val<4:0> = bits(5) UNKNOWN;
        R[d] = psr_val;

mrs