vcvt

Vector Convert (Fixed Point)

VCVT<c>.<Td>.<Tm> <Qd>, <Qm>, #<fbits>

Converts between floating-point and fixed-point.

Details

Converts between floating-point and fixed-point formats in 128-bit SIMD registers with a specified number of fractional bits. This is a NEON instruction that operates element-wise on the vector operands. No condition flags are affected.

Pseudocode Operation

if ConditionPassed() then
  for i = 0 to elements-1
    if Tm == F32 then
      Qd[i] = FixedPointConvert(Qm[i], fbits)
    else
      Qd[i] = FloatingPointConvert(Qm[i], fbits)

Example

VCVT.Td.Tm q0, q2, #8

Encoding

Binary Layout

cond

11101

imm4

Format VFP Convert

Opcode 0x0EBE0A40

Extension VFP (Float)

Operands

Qd
Destination 128-bit SIMD register
Qm
Second source 128-bit SIMD register
fbits
Number of fractional bits

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0xF3B60640	VCVT{<c>}{<q>}.BF16.F32 <Dd>, <Qm>	A32	111100111 \| D \| 11 \| 01 \| 10 \| Vd \| 0 \| 1100 \| 1 \| M \| 0 \| Vm
0xFFB60640	VCVT{<c>}{<q>}.BF16.F32 <Dd>, <Qm>	T32	111111111 \| D \| 11 \| 01 \| 10 \| Vd \| 0 \| 1100 \| 1 \| M \| 0 \| Vm
0x0EB70AC0	VCVT{<c>}{<q>}.F64.F32 <Dd>, <Sm>	A32	cond \| 11101 \| D \| 11 \| 0 \| 111 \| Vd \| 10 \| size \| 1 \| 1 \| M \| 0 \| Vm
0x0EB70AC0	VCVT{<c>}{<q>}.F32.F64 <Sd>, <Dm>	A32	cond \| 11101 \| D \| 11 \| 0 \| 111 \| Vd \| 10 \| size \| 1 \| 1 \| M \| 0 \| Vm
0xEEB70AC0	VCVT{<c>}{<q>}.F64.F32 <Dd>, <Sm>	T32	111011101 \| D \| 11 \| 0 \| 111 \| Vd \| 10 \| size \| 1 \| 1 \| M \| 0 \| Vm
0xEEB70AC0	VCVT{<c>}{<q>}.F32.F64 <Sd>, <Dm>	T32	111011101 \| D \| 11 \| 0 \| 111 \| Vd \| 10 \| size \| 1 \| 1 \| M \| 0 \| Vm
0xF3B20700	VCVT{<c>}{<q>}.F32.F16 <Qd>, <Dm>	A32	111100111 \| D \| 11 \| size \| 10 \| Vd \| 0 \| 11 \| 1 \| 0 \| 0 \| M \| 0 \| Vm
0xF3B20600	VCVT{<c>}{<q>}.F16.F32 <Dd>, <Qm>	A32	111100111 \| D \| 11 \| size \| 10 \| Vd \| 0 \| 11 \| 0 \| 0 \| 0 \| M \| 0 \| Vm
0xFFB20700	VCVT{<c>}{<q>}.F32.F16 <Qd>, <Dm>	T32	111111111 \| D \| 11 \| size \| 10 \| Vd \| 0 \| 11 \| 1 \| 0 \| 0 \| M \| 0 \| Vm
0xFFB20600	VCVT{<c>}{<q>}.F16.F32 <Dd>, <Qm>	T32	111111111 \| D \| 11 \| size \| 10 \| Vd \| 0 \| 11 \| 0 \| 0 \| 0 \| M \| 0 \| Vm
0xF3B30600	VCVT{<c>}{<q>}.<dt1>.<dt2> <Dd>, <Dm>	A32	111100111 \| D \| 11 \| size \| 11 \| Vd \| 0 \| 11 \| op \| 0 \| M \| 0 \| Vm
0xF3B30640	VCVT{<c>}{<q>}.<dt1>.<dt2> <Qd>, <Qm>	A32	111100111 \| D \| 11 \| size \| 11 \| Vd \| 0 \| 11 \| op \| 1 \| M \| 0 \| Vm
0xFFB30600	VCVT{<c>}{<q>}.<dt1>.<dt2> <Dd>, <Dm>	T32	111111111 \| D \| 11 \| size \| 11 \| Vd \| 0 \| 11 \| op \| 0 \| M \| 0 \| Vm
0xFFB30640	VCVT{<c>}{<q>}.<dt1>.<dt2> <Qd>, <Qm>	T32	111111111 \| D \| 11 \| size \| 11 \| Vd \| 0 \| 11 \| op \| 1 \| M \| 0 \| Vm

Description

Convert between floating-point and fixed-point converts a value in a register from floating-point to fixed-point, or from fixed-point to floating-point. Software can specify the fixed-point value as either signed or unsigned. The fixed-point value can be 16-bit or 32-bit. Conversions from fixed-point values take their operand from the low-order bits of the source register and ignore any remaining bits. Signed conversions to fixed-point values sign-extend the result value to the destination register width. Unsigned conversions to fixed-point values zero-extend the result value to the destination register width. The floating-point to fixed-point operation uses the Round towards Zero rounding mode. The fixed-point to floating-point operation uses the Round to Nearest rounding mode. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckVFPEnabled(TRUE);
    if to_fixed then
        bits(size) result;
        case fp_size of
            when 16
                result = FPToFixed(S[d]<15:0>, frac_bits, unsigned, FPSCR[],
                                   FPRounding_ZERO, size);
                S[d] = Extend(result, 32, unsigned);
            when 32
                result = FPToFixed(S[d], frac_bits, unsigned, FPSCR[], FPRounding_ZERO, size);
                S[d] = Extend(result, 32, unsigned);
            when 64
                result = FPToFixed(D[d], frac_bits, unsigned, FPSCR[], FPRounding_ZERO, size);
                D[d] = Extend(result, 64, unsigned);
    else
        case fp_size of
            when 16
                bits(16) fp16 = FixedToFP(S[d]<size-1:0>, frac_bits, unsigned, FPSCR[],
                                          FPRounding_TIEEVEN, 16);
                S[d] = Zeros(16):fp16;
            when 32
                S[d] = FixedToFP(S[d]<size-1:0>, frac_bits, unsigned, FPSCR[],
                                 FPRounding_TIEEVEN, 32);
            when 64
                D[d] = FixedToFP(D[d]<size-1:0>, frac_bits, unsigned, FPSCR[],
                                 FPRounding_TIEEVEN, 64);