eor

Vector Bitwise Exclusive OR

EOR <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Bitwise XOR of two vectors.

Pseudocode Operation

for i = 0 to (128 >> (if Q then 0 else 1)) - 1:
  Vd[i] ← Vn[i] XOR Vm[i];

Example

EOR v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout

01110

28:24

23:22

20:16

00011

15:11

9:5

4:0

Format SIMD Three Register

Opcode 0x2E201C00

Extension NEON (SIMD)

Operands

Vd
Destination SIMD/FP vector register
Vn
First source SIMD/FP vector register
Vm
Second source SIMD/FP vector register

Other forms of eor

eor Bitwise Exclusive OR (Immediate)
eor Bitwise Exclusive OR (Register)
eor SVE Bitwise Exclusive OR (Predicated)
eor Exclusive OR (A32)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x2E201C00	EOR <Vd>.<T>, <Vn>.<T>, <Vm>.<T>	A64	0 \| Q \| 1 \| 01110 \| 00 \| 1 \| Rm \| 00011 \| 1 \| Rn \| Rd
0x52000000	EOR <Wd\|WSP>, <Wn>, #<imm>	A64	0 \| 10 \| 100100 \| 0 \| immr \| imms \| Rn \| Rd
0xD2000000	EOR <Xd\|SP>, <Xn>, #<imm>	A64	1 \| 10 \| 100100 \| N \| immr \| imms \| Rn \| Rd
0x4A000000	EOR <Wd>, <Wn>, <Wm>{, <shift> #<amount>}	A64	0 \| 10 \| 01010 \| shift \| 0 \| Rm \| imm6 \| Rn \| Rd
0xCA000000	EOR <Xd>, <Xn>, <Xm>{, <shift> #<amount>}	A64	1 \| 10 \| 01010 \| shift \| 0 \| Rm \| imm6 \| Rn \| Rd
0x25004200	EOR <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B	A64	00100101 \| 0 \| 0 \| 00 \| Pm \| 01 \| Pg \| 1 \| Pn \| 0 \| Pd
0x04190000	EOR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>	A64	00000100 \| size \| 011 \| 00 \| 1 \| 000 \| Pg \| Zm \| Zdn
0x05400000	EOR <Zdn>.<T>, <Zdn>.<T>, #<const>	A64	00000101 \| 0 \| 1 \| 0000 \| imm13 \| Zdn
0x04A03000	EOR <Zd>.D, <Zn>.D, <Zm>.D	A64	00000100 \| 1 \| 0 \| 1 \| Zm \| 001100 \| Zn \| Zd

Description

Bitwise Exclusive-OR (vector). This instruction performs a bitwise exclusive-OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1;
bits(datasize) operand2;
bits(datasize) operand3;
bits(datasize) operand4 = V[n, datasize];

operand1 = V[m, datasize];
operand2 = Zeros(datasize);
operand3 = Ones(datasize);
V[d, datasize] = operand1 EOR ((operand2 EOR operand4) AND operand3);

eor