ldrsh.w

Load Register Signed Halfword (Wide)

LDRSH.W <Rt>, [<Rn>, #<imm>]

Thumb-2 32-bit Load Signed Halfword.

Details

The Load Register Signed Halfword instruction thumb-2 32-bit Load Signed Halfword.

Pseudocode Operation

Rt ← Memory[address]

Example

LDRSH.W r3, [r1, #16]

Encoding

Binary Layout
111110011011
Rn
Rt
imm12
 
Format Thumb Load
Opcode 0xF9B00000
Extension T32 (Thumb2)

Operands

  • Rt
    Transfer general-purpose register (load/store)
  • Rn
    First source / base general-purpose register
  • imm
    Signed immediate value