vmax

Vector Maximum

VMAX<c>.<dt> <Qd>, <Qn>, <Qm>

Selects maximum value from elements.

Details

Compares corresponding lanes of two 128-bit NEON vectors and stores the maximum value in each lane of the destination. The comparison is performed element-wise according to the data type (signed or unsigned integer). No condition flags are affected. This is an ARMv7 Advanced SIMD instruction, executable in both A32 and T32 states.

Pseudocode Operation

for each lane i of size specified by dt
  if Qn[i] > Qm[i]
    Qd[i] ← Qn[i]
  else
    Qd[i] ← Qm[i]

Example

VMAX.dt q0, q1, q2

Encoding

Binary Layout
1111001
U
0
D
size
Vn
Vd
0110
N
0
M
0
Vm
 
Format NEON 3-Reg
Opcode 0xF2000600
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2000F00 VMAX{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> A32 1111001 | 0 | 0 | D | 0 | sz | Vn | Vd | 1111 | N | 0 | M | 0 | Vm
0xF2000F40 VMAX{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> A32 1111001 | 0 | 0 | D | 0 | sz | Vn | Vd | 1111 | N | 1 | M | 0 | Vm
0xEF000F00 VMAX{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> T32 111 | 0 | 11110 | D | 0 | sz | Vn | Vd | 1111 | N | 0 | M | 0 | Vm
0xEF000F40 VMAX{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> T32 111 | 0 | 11110 | D | 0 | sz | Vn | Vd | 1111 | N | 1 | M | 0 | Vm
0xF2000600 VMAX{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> A32 1111001 | U | 0 | D | size | Vn | Vd | 0110 | N | 0 | M | 0 | Vm
0xF2000640 VMAX{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> A32 1111001 | U | 0 | D | size | Vn | Vd | 0110 | N | 1 | M | 0 | Vm
0xEF000600 VMAX{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> T32 111 | U | 11110 | D | size | Vn | Vd | 0110 | N | 0 | M | 0 | Vm
0xEF000640 VMAX{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> T32 111 | U | 11110 | D | size | Vn | Vd | 0110 | N | 1 | M | 0 | Vm

Description

Vector Maximum compares corresponding elements in two vectors, and copies the larger of each pair into the corresponding element in the destination vector. The operand vector elements can be any one of: The result vector elements are the same size as the operand vector elements. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        for e = 0 to elements-1
            op1 = Int(Elem[D[n+r],e,esize], unsigned);
            op2 = Int(Elem[D[m+r],e,esize], unsigned);
            result = if maximum then Max(op1,op2) else Min(op1,op2);
            Elem[D[d+r],e,esize] = result<esize-1:0>;