umull

Unsigned Multiply Long (A32)

UMULL{S}<c> <RdLo>, <RdHi>, <Rn>, <Rm>

Unsigned (Rn * Rm) -> 64-bit Result.

Pseudocode Operation

result ← Rn[31:0] × Rm[31:0];  // unsigned 64-bit product
RdLo ← result[31:0];
RdHi ← result[63:32];
if S then
  N ← RdHi[31];
  Z ← (result == 0);
endif;

Example

UMULL r1, r0, r1, r2

Encoding

Binary Layout

cond

31:28

0000

27:24

100

23:21

RdHi

19:16

RdLo

15:12

11:8

1001

7:4

3:0

Format Multiply

Opcode 0x00800090

Extension A32 (Base)

Operands

RdLo
Low
RdHi
High
Rn
First source / base general-purpose register
Rm
Second source / offset general-purpose register

Other forms of umull

umull Unsigned Multiply Long (Thumb)
umull Unsigned Multiply Long

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x00800090	UMULL{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>		A32		cond \| 0000 \| 100 \| 0 \| RdHi \| RdLo \| Rm \| 1001 \| Rn
0xFBA00000	UMULL{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>		T32		111110111 \| 010 \| Rn \| RdLo \| RdHi \| 0000 \| Rm

Description

Unsigned Multiply Long multiplies two 32-bit unsigned values to produce a 64-bit result. In A32 instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many implementations.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    result = UInt(R[n]) * UInt(R[m]);
    R[dHi] = result<63:32>;
    R[dLo] = result<31:0>;
    if setflags then
        PSTATE.N = result<63>;
        PSTATE.Z = IsZeroBit(result<63:0>);
        // PSTATE.C, PSTATE.V unchanged