vmsr
Move Register to VFP System Register
VMSR<c> <spec_reg>, <Rt>
Writes to a VFP system register.
Pseudocode Operation
if ConditionPassed(cond) then
if Rt == 15 then
FPSCR[31:28] ← APSR_nzcv
else
FPSCR ← Rt
Example
VMSR nzcv, r3
Encoding
Binary Layout
cond
31:28
1110111
27:21
0
20
reg
19:16
Rt
15:12
1010
11:8
0
7
0
6
0
5
1
4
0
3
0
2
0
1
0
0
Operands
-
spec_reg
FPSCR -
Rt
Transfer general-purpose register (load/store)
Related
More in VFP (System)
Reference
View in Arm A64 ISA Reference ↗
Arm AArch32 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x0EE00A10 | VMSR{<c>}{<q>} <spec_reg>, <Rt> | A32 | cond | 1110111 | 0 | reg | Rt | 1010 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | ||
| 0xEEE00A10 | VMSR{<c>}{<q>} <spec_reg>, <Rt> | T32 | 11101110111 | 0 | reg | Rt | 1010 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
Description
Move general-purpose register to SIMD&FP Special register moves the value of a general-purpose register to a floating-point System register. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support. When these settings permit the execution of Advanced SIMD and floating-point instructions:
Operation
if ConditionPassed() then
EncodingSpecificOperations();
if reg == '0001' then // FPSCR
CheckVFPEnabled(TRUE);
FPSCR = R[t];
elsif PSTATE.EL == EL0 then
UNDEFINED; // Non-FPSCR registers accessible only at PL1 or above
else
CheckVFPEnabled(FALSE); // Non-FPSCR registers are not affected by FPEXC.EN
case reg of
when '0000' // VMSR access to FPSID is ignored
when '1000'
FPEXC = R[t];
otherwise
Unreachable(); // Dealt with above or in encoding-specific pseudocode