fcadd

SVE Floating-Point Complex Add

FCADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>, #<rot>

Performs complex addition with rotation.

Details

SVE floating-point complex add: performs a predicate-masked complex addition of Zdn and Zm with a 90° or 270° rotation applied to Zm before addition. For rot=90, computes Zdn + i*Zm; for rot=270, computes Zdn - i*Zm. Elements where the predicate is false are left unchanged. Floating-point exceptions are signaled per IEEE 754. This is an SVE-only instruction.

Pseudocode Operation

for i = 0 to VL-1
  if Pg[i] == '1' then
    rotated ← RotateComplex(Zm[i], rot)
    Zdn[i] ← FPAdd(Zdn[i], rotated)
  // else Zdn[i] unchanged

Example

FCADD z0.s.T, p0/m/M, z0.s.T, z2.s.T, #rot

Encoding

Binary Layout
01100100
size
00000
rot
100
Pg
Zm
Zdn
 
Format SVE FP Complex
Opcode 0x64008000
Extension SVE

Operands

  • Zdn
    Combined destination/source scalable vector register (SVE)
  • Pg
    Mask
  • Zm
    Second source scalable vector register (SVE)
  • rot
    Rotation (90, 270)

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x2E00E400 FCADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<rotate> A64 0 | Q | 1 | 01110 | size | 0 | Rm | 111 | rot | 01 | Rn | Rd
0x64008000 FCADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>, <const> A64 01100100 | size | 00000 | rot | 100 | Pg | Zm | Zdn

Description

Add the real and imaginary components of the active floating-point complex numbers from the first source vector to the complex numbers from the second source vector which have first been rotated by 90 or 270 degrees in the direction from the positive real axis towards the positive imaginary axis, when considered in polar representation, equivalent to multiplying the complex numbers in the second source vector by ±j beforehand. Destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified. Each complex number is represented in a vector register as an even/odd pair of elements with the real part in the even-numbered element and the imaginary part in the odd-numbered element.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer pairs = VL DIV (2 * esize);
bits(PL) mask = P[g, PL];
bits(VL) operand1 = Z[dn, VL];
bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL);
bits(VL) result;

for p = 0 to pairs-1
    acc_r = Elem[operand1, 2 * p + 0, esize];
    acc_i = Elem[operand1, 2 * p + 1, esize];
    if ActivePredicateElement(mask, 2 * p + 0, esize) then
        elt2_i = Elem[operand2, 2 * p + 1, esize];
        if sub_i then elt2_i = FPNeg(elt2_i, FPCR);
        acc_r = FPAdd(acc_r, elt2_i, FPCR);
    if ActivePredicateElement(mask, 2 * p + 1, esize) then
        elt2_r = Elem[operand2, 2 * p + 0, esize];
        if sub_r then elt2_r = FPNeg(elt2_r, FPCR);
        acc_i = FPAdd(acc_i, elt2_r, FPCR);
    Elem[result, 2 * p + 0, esize] = acc_r;
    Elem[result, 2 * p + 1, esize] = acc_i;

Z[dn, VL] = result;