prfm
Prefetch Memory (Immediate)
PRFM <prfop>, [<Xn|SP>, #<pimm>]
Signals the memory system to prefetch data into cache.
Details
Prefetch Memory (Immediate) signals the memory system to prefetch data from an address calculated by adding a scaled 12-bit immediate offset to a base register. This is a hint instruction that does not architecturally affect register state or condition flags. Execution is AArch64-only and no exceptions are generated for invalid addresses.
Pseudocode Operation
address ← Xn|SP + (imm12 << 3); Prefetch(address, prfop);
Example
PRFM prfop, [x1, #16]
Encoding
Binary Layout
11
111
0
01
10
imm12
Rn
Rt
Operands
-
prfop
Type (PLDL1KEEP, etc) -
Xn
Base Addr -
pimm
Positive immediate offset
Reference (Arm A64 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0xF9800000 | PRFM (<prfop>|#<imm5>), [<Xn|SP>{, #<pimm>}] | A64 | 11 | 111 | 0 | 01 | 10 | imm12 | Rn | Rt | ||
| 0xD8000000 | PRFM (<prfop>|#<imm5>), <label> | A64 | 11 | 011 | 0 | 00 | imm19 | Rt | ||
| 0xF8A04800 | PRFM (<prfop>|#<imm5>), [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}] | A64 | 11 | 111 | 0 | 00 | 10 | 1 | Rm | option | S | 10 | Rn | Rt |
Description
Prefetch Memory (immediate) signals the memory system that data memory accesses from a specified address are likely to occur in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as preloading the cache line containing the specified address into one or more caches.
The effect of a PRFM instruction is IMPLEMENTATION DEFINED. For more information, see Prefetch memory.
For information about memory accesses, see Load/Store addressing modes.
Operation
bits(64) address;
boolean privileged = PSTATE.EL != EL0;
AccessDescriptor accdesc = CreateAccDescGPR(MemOp_PREFETCH, FALSE, privileged, FALSE);
if n == 31 then
address = SP[];
else
address = X[n, 64];
address = GenerateAddress(address, offset, accdesc);
Prefetch(address, t<4:0>);