prfm

Prefetch Memory (Immediate)

PRFM <prfop>, [<Xn|SP>, #<pimm>]

Signals the memory system to prefetch data into cache.

Pseudocode Operation

address ← Xn|SP + (imm12 << 3); Prefetch(address, prfop);

Example

PRFM prfop, [x1, #16]

Encoding

Binary Layout
11
31:30
111
29:27
0
26
01
25:24
10
23:22
imm12
21:10
Rn
9:5
Rt
4:0
 
Format Load/Store Imm
Opcode 0xF9800000
Extension Base

Operands

  • prfop
    Type (PLDL1KEEP, etc)
  • Xn
    Base Addr
  • pimm
    Positive immediate offset

Related

Other forms of prfm

  • prfm Prefetch Memory (Literal)
  • prfm Prefetch Memory (Register)

Across architectures

Cache Prefetch Hint : how x86, ARM, RISC-V, and PowerISA each do this.

More in Base

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF9800000 PRFM (<prfop>|#<imm5>), [<Xn|SP>{, #<pimm>}] A64 11 | 111 | 0 | 01 | 10 | imm12 | Rn | Rt
0xD8000000 PRFM (<prfop>|#<imm5>), <label> A64 11 | 011 | 0 | 00 | imm19 | Rt
0xF8A04800 PRFM (<prfop>|#<imm5>), [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}] A64 11 | 111 | 0 | 00 | 10 | 1 | Rm | option | S | 10 | Rn | Rt

Description

Prefetch Memory (immediate) signals the memory system that data memory accesses from a specified address are likely to occur in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as preloading the cache line containing the specified address into one or more caches. The effect of a PRFM instruction is IMPLEMENTATION DEFINED. For more information, see Prefetch memory. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address;

boolean privileged = PSTATE.EL != EL0;
AccessDescriptor accdesc = CreateAccDescGPR(MemOp_PREFETCH, FALSE, privileged, FALSE);

if n == 31 then
    address = SP[];
else
    address = X[n, 64];

address = GenerateAddress(address, offset, accdesc);

Prefetch(address, t<4:0>);