vmrs

Move VFP System Register to Register

VMRS<c> <Rt>, <spec_reg>

Reads a VFP system register (like FPSCR).

Details

Reads a VFP system register (typically FPSCR) and transfers its value to a general-purpose register or the APSR condition flags. This is an A32/T32 instruction that executes conditionally. If Rt is R15, the N, Z, C, V flags are updated from FPSCR bits; otherwise no flags are modified.

Pseudocode Operation

if ConditionPassed(cond) then
  if Rt == 15 then
    APSR_nzcv ← FPSCR[31:28]
  else
    Rt ← FPSCR

Example

VMRS r3, nzcv

Encoding

Binary Layout
cond
1110111
1
reg
Rt
1010
0
0
0
1
0
0
0
0
 
Format VFP System
Opcode 0x0EF00A10
Extension VFP (System)

Operands

  • Rt
    Dest (or APSR_nzcv)
  • spec_reg
    FPSCR

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0EF00A10 VMRS{<c>}{<q>} <Rt>, <spec_reg> A32 cond | 1110111 | 1 | reg | Rt | 1010 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0
0xEEF00A10 VMRS{<c>}{<q>} <Rt>, <spec_reg> T32 11101110111 | 1 | reg | Rt | 1010 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0

Description

Move SIMD&FP Special register to general-purpose register moves the value of an Advanced SIMD and floating-point System register to a general-purpose register. When the specified System register is the FPSCR, a form of the instruction transfers the FPSCR.{N, Z, C, V} condition flags to the APSR.{N, Z, C, V} condition flags. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support. When these settings permit the execution of Advanced SIMD and floating-point instructions, if the specified floating-point System register is not the FPSCR, the instruction is undefined if executed in User mode. In an implementation that includes EL2, when HCR.TID0 is set to 1, any VMRS access to FPSID from a Non-secure EL1 mode that would be permitted if HCR.TID0 was set to 0 generates a Hyp Trap exception. For more information, see ID group 0, Primary device identification registers. For simplicity, the VMRS pseudocode does not show the possible trap to Hyp mode.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    if reg == '0001' then                 // FPSCR
        CheckVFPEnabled(TRUE);
        if t == 15 then
            PSTATE.<N,Z,C,V> = FPSR.<N,Z,C,V>;
        else
            R[t] = FPSCR;
    elsif PSTATE.EL == EL0 then
        UNDEFINED;                        // Non-FPSCR registers accessible only at PL1 or above
    else
        CheckVFPEnabled(FALSE);           // Non-FPSCR registers are not affected by FPEXC.EN
        AArch32.CheckAdvSIMDOrFPRegisterTraps(reg);
        case reg of
            when '0000'  R[t] = FPSID;
            when '0101'  R[t] = MVFR2;
            when '0110'  R[t] = MVFR1;
            when '0111'  R[t] = MVFR0;
            when '1000'  R[t] = FPEXC;
            otherwise    Unreachable();   // Dealt with above or in encoding-specific pseudocode