vmls

Vector Multiply Subtract

VMLS<c>.<dt> <Qd>, <Qn>, <Qm>

Multiplies and subtracts from accumulator.

Details

Multiplies corresponding elements from two source registers and subtracts the products from the accumulator. Performs Qd ← Qd - (Qn × Qm) for each element. The sz field specifies 16-bit or 32-bit element width. Condition flags are unaffected. This is an A32/T32 NEON instruction with no privilege restrictions.

Pseudocode Operation

for i = 0 to (128 / element_width) - 1:
  product ← Qn[i] × Qm[i]
  Qd[i] ← Qd[i] - product

Example

VMLS.dt q0, q1, q2

Encoding

Binary Layout
1111001
0
0
D
1
sz
Vn
Vd
1101
N
1
M
1
Vm
 
Format NEON 3-Reg
Opcode 0xF2200D50
Extension NEON (SIMD)

Operands

  • Qd
    Dest/Acc
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2200D10 VMLS{<c>}{<q>}.<dt> <Dd>, <Dn>, <Dm> A32 1111001 | 0 | 0 | D | 1 | sz | Vn | Vd | 1101 | N | 0 | M | 1 | Vm
0xF2200D50 VMLS{<c>}{<q>}.<dt> <Qd>, <Qn>, <Qm> A32 1111001 | 0 | 0 | D | 1 | sz | Vn | Vd | 1101 | N | 1 | M | 1 | Vm
0x0E000940 VMLS{<c>}{<q>}.F16 <Sd>, <Sn>, <Sm> A32 cond | 1110 | 0 | D | 00 | Vn | Vd | 10 | 01 | N | 1 | M | 0 | Vm
0x0E000A40 VMLS{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm> A32 cond | 1110 | 0 | D | 00 | Vn | Vd | 10 | 10 | N | 1 | M | 0 | Vm
0x0E000B40 VMLS{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm> A32 cond | 1110 | 0 | D | 00 | Vn | Vd | 10 | 11 | N | 1 | M | 0 | Vm
0xEF200D10 VMLS{<c>}{<q>}.<dt> <Dd>, <Dn>, <Dm> T32 111 | 0 | 11110 | D | 1 | sz | Vn | Vd | 1101 | N | 0 | M | 1 | Vm
0xEF200D50 VMLS{<c>}{<q>}.<dt> <Qd>, <Qn>, <Qm> T32 111 | 0 | 11110 | D | 1 | sz | Vn | Vd | 1101 | N | 1 | M | 1 | Vm
0xEE000940 VMLS{<c>}{<q>}.F16 <Sd>, <Sn>, <Sm> T32 11101110 | 0 | D | 00 | Vn | Vd | 10 | 01 | N | 1 | M | 0 | Vm
0xEE000A40 VMLS{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm> T32 11101110 | 0 | D | 00 | Vn | Vd | 10 | 10 | N | 1 | M | 0 | Vm
0xEE000B40 VMLS{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm> T32 11101110 | 0 | D | 00 | Vn | Vd | 10 | 11 | N | 1 | M | 0 | Vm
0xF3000900 VMLS{<c>}{<q>}.<dt> <Dd>, <Dn>, <Dm> A32 1111001 | 1 | 0 | D | size | Vn | Vd | 1001 | N | 0 | M | 0 | Vm
0xF3000940 VMLS{<c>}{<q>}.<dt> <Qd>, <Qn>, <Qm> A32 1111001 | 1 | 0 | D | size | Vn | Vd | 1001 | N | 1 | M | 0 | Vm
0xFF000900 VMLS{<c>}{<q>}.<dt> <Dd>, <Dn>, <Dm> T32 111 | 1 | 11110 | D | size | Vn | Vd | 1001 | N | 0 | M | 0 | Vm
0xFF000940 VMLS{<c>}{<q>}.<dt> <Qd>, <Qn>, <Qm> T32 111 | 1 | 11110 | D | size | Vn | Vd | 1001 | N | 1 | M | 0 | Vm

Description

Vector Multiply Subtract multiplies corresponding elements in two vectors, subtracts the products from corresponding elements of the destination vector, and places the results in the destination vector. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDOrVFPEnabled(TRUE, advsimd);
    if advsimd then  // Advanced SIMD instruction
        for r = 0 to regs-1
            for e = 0 to elements-1
                product = FPMul(Elem[D[n+r],e,esize], Elem[D[m+r],e,esize], StandardFPSCRValue());
                addend = if add then product else FPNeg(product);
                Elem[D[d+r],e,esize] = FPAdd(Elem[D[d+r],e,esize], addend, StandardFPSCRValue());
    else             // VFP instruction
        case esize of
            when 16
                addend16 = (if add then FPMul(S[n]<15:0>, S[m]<15:0>, FPSCR[])
                            else FPNeg(FPMul(S[n]<15:0>, S[m]<15:0>, FPSCR[])));
                S[d] = Zeros(16) : FPAdd(S[d]<15:0>, addend16, FPSCR[]);
            when 32
                addend32 = (if add then FPMul(S[n], S[m], FPSCR[])
                            else FPNeg(FPMul(S[n], S[m], FPSCR[])));
                S[d] = FPAdd(S[d], addend32, FPSCR[]);
            when 64
                addend64 = (if add then FPMul(D[n], D[m], FPSCR[])
                            else FPNeg(FPMul(D[n], D[m], FPSCR[])));
                D[d] = FPAdd(D[d], addend64, FPSCR[]);