vabs
Vector Absolute Value (Double)
VABS<c>.F64 <Dd>, <Dm>
Absolute value of double-precision register.
Pseudocode Operation
Dd.sign ← 0; Dd.exponent ← Dm.exponent; Dd.fraction ← Dm.fraction;Example
VABS.F64 d0, d2
Encoding
Binary Layout
cond
31:28
11101
27:23
D
22
11
21:20
0
19
000
18:16
Vd
15:12
10
11:10
11
9:8
1
7
1
6
M
5
0
4
Vm
3:0
Operands
-
Dd
Destination 64-bit SIMD/FP register -
Dm
Second source 64-bit SIMD/FP register
Reference
View in Arm A64 ISA Reference ↗
Arm AArch32 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0xF3B10300 | VABS{<c>}{<q>}.<dt> <Dd>, <Dm> | A32 | 111100111 | D | 11 | size | 01 | Vd | 0 | F | 110 | 0 | M | 0 | Vm | ||
| 0xF3B10340 | VABS{<c>}{<q>}.<dt> <Qd>, <Qm> | A32 | 111100111 | D | 11 | size | 01 | Vd | 0 | F | 110 | 1 | M | 0 | Vm | ||
| 0x0EB009C0 | VABS{<c>}{<q>}.F16 <Sd>, <Sm> | A32 | cond | 11101 | D | 11 | 0 | 000 | Vd | 10 | 01 | 1 | 1 | M | 0 | Vm | ||
| 0x0EB00AC0 | VABS{<c>}{<q>}.F32 <Sd>, <Sm> | A32 | cond | 11101 | D | 11 | 0 | 000 | Vd | 10 | 10 | 1 | 1 | M | 0 | Vm | ||
| 0x0EB00BC0 | VABS{<c>}{<q>}.F64 <Dd>, <Dm> | A32 | cond | 11101 | D | 11 | 0 | 000 | Vd | 10 | 11 | 1 | 1 | M | 0 | Vm | ||
| 0xFFB10300 | VABS{<c>}{<q>}.<dt> <Dd>, <Dm> | T32 | 111111111 | D | 11 | size | 01 | Vd | 0 | F | 110 | 0 | M | 0 | Vm | ||
| 0xFFB10340 | VABS{<c>}{<q>}.<dt> <Qd>, <Qm> | T32 | 111111111 | D | 11 | size | 01 | Vd | 0 | F | 110 | 1 | M | 0 | Vm | ||
| 0xEEB009C0 | VABS{<c>}{<q>}.F16 <Sd>, <Sm> | T32 | 111011101 | D | 11 | 0 | 000 | Vd | 10 | 01 | 1 | 1 | M | 0 | Vm | ||
| 0xEEB00AC0 | VABS{<c>}{<q>}.F32 <Sd>, <Sm> | T32 | 111011101 | D | 11 | 0 | 000 | Vd | 10 | 10 | 1 | 1 | M | 0 | Vm | ||
| 0xEEB00BC0 | VABS{<c>}{<q>}.F64 <Dd>, <Dm> | T32 | 111011101 | D | 11 | 0 | 000 | Vd | 10 | 11 | 1 | 1 | M | 0 | Vm |
Description
Vector Absolute takes the absolute value of each element in a vector, and places the results in a second vector. The floating-point version only clears the sign bit. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDOrVFPEnabled(TRUE, advsimd);
if advsimd then // Advanced SIMD instruction
for r = 0 to regs-1
for e = 0 to elements-1
if floating_point then
Elem[D[d+r],e,esize] = FPAbs(Elem[D[m+r],e,esize]);
else
result = Abs(SInt(Elem[D[m+r],e,esize]));
Elem[D[d+r],e,esize] = result<esize-1:0>;
else // VFP instruction
case esize of
when 16 S[d] = Zeros(16) : FPAbs(S[m]<15:0>);
when 32 S[d] = FPAbs(S[m]);
when 64 D[d] = FPAbs(D[m]);