vmla

Vector Multiply Accumulate

VMLA<c>.<dt> <Qd>, <Qn>, <Qm>

Multiplies and adds to accumulator.

Pseudocode Operation

for i = 0 to (128 / element_width) - 1:
  product ← Qn[i] × Qm[i]
  Qd[i] ← Qd[i] + product

Example

VMLA.dt q0, q1, q2

Encoding

Binary Layout
1111001
31:25
0
24
0
23
D
22
size
21:20
Vn
19:16
Vd
15:12
1001
11:8
N
7
0
6
M
5
0
4
Vm
3:0
 
Format NEON 3-Reg
Opcode 0xF2000900
Extension NEON (SIMD)

Operands

  • Qd
    Dest/Acc
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Related

Other forms of vmla

  • vmla Vector Multiply Accumulate (VFP)

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2000D10 VMLA{<c>}{<q>}.<dt> <Dd>, <Dn>, <Dm> A32 1111001 | 0 | 0 | D | 0 | sz | Vn | Vd | 1101 | N | 0 | M | 1 | Vm
0xF2000D50 VMLA{<c>}{<q>}.<dt> <Qd>, <Qn>, <Qm> A32 1111001 | 0 | 0 | D | 0 | sz | Vn | Vd | 1101 | N | 1 | M | 1 | Vm
0x0E000900 VMLA{<c>}{<q>}.F16 <Sd>, <Sn>, <Sm> A32 cond | 1110 | 0 | D | 00 | Vn | Vd | 10 | 01 | N | 0 | M | 0 | Vm
0x0E000A00 VMLA{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm> A32 cond | 1110 | 0 | D | 00 | Vn | Vd | 10 | 10 | N | 0 | M | 0 | Vm
0x0E000B00 VMLA{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm> A32 cond | 1110 | 0 | D | 00 | Vn | Vd | 10 | 11 | N | 0 | M | 0 | Vm
0xEF000D10 VMLA{<c>}{<q>}.<dt> <Dd>, <Dn>, <Dm> T32 111 | 0 | 11110 | D | 0 | sz | Vn | Vd | 1101 | N | 0 | M | 1 | Vm
0xEF000D50 VMLA{<c>}{<q>}.<dt> <Qd>, <Qn>, <Qm> T32 111 | 0 | 11110 | D | 0 | sz | Vn | Vd | 1101 | N | 1 | M | 1 | Vm
0xEE000900 VMLA{<c>}{<q>}.F16 <Sd>, <Sn>, <Sm> T32 11101110 | 0 | D | 00 | Vn | Vd | 10 | 01 | N | 0 | M | 0 | Vm
0xEE000A00 VMLA{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm> T32 11101110 | 0 | D | 00 | Vn | Vd | 10 | 10 | N | 0 | M | 0 | Vm
0xEE000B00 VMLA{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm> T32 11101110 | 0 | D | 00 | Vn | Vd | 10 | 11 | N | 0 | M | 0 | Vm
0xF2000900 VMLA{<c>}{<q>}.<dt> <Dd>, <Dn>, <Dm> A32 1111001 | 0 | 0 | D | size | Vn | Vd | 1001 | N | 0 | M | 0 | Vm
0xF2000940 VMLA{<c>}{<q>}.<dt> <Qd>, <Qn>, <Qm> A32 1111001 | 0 | 0 | D | size | Vn | Vd | 1001 | N | 1 | M | 0 | Vm
0xEF000900 VMLA{<c>}{<q>}.<dt> <Dd>, <Dn>, <Dm> T32 111 | 0 | 11110 | D | size | Vn | Vd | 1001 | N | 0 | M | 0 | Vm
0xEF000940 VMLA{<c>}{<q>}.<dt> <Qd>, <Qn>, <Qm> T32 111 | 0 | 11110 | D | size | Vn | Vd | 1001 | N | 1 | M | 0 | Vm

Description

Vector Multiply Accumulate multiplies corresponding elements in two vectors, and adds the products to the corresponding elements of the destination vector. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        for e = 0 to elements-1
            product = Int(Elem[Din[n+r],e,esize],unsigned) * Int(Elem[Din[m+r],e,esize],unsigned);
            addend = if add then product else -product;
            if long_destination then
                Elem[Q[d>>1],e,2*esize] = Elem[Qin[d>>1],e,2*esize] + addend;
            else
                Elem[D[d+r],e,esize] = Elem[Din[d+r],e,esize] + addend;