vqsub

Vector Saturating Subtract

VQSUB<c>.<dt> <Qd>, <Qn>, <Qm>

Subtracts elements with saturation.

Details

Subtracts the second operand from the first with saturation. If the result overflows or underflows, it is saturated to the data type's maximum or minimum representable value. No condition flags are affected; saturation status is not reflected in APSR. Execution is available in both A32 and T32 instruction sets via NEON.

Pseudocode Operation

for i = 0 to elements-1
  Qd[i] ← SatQ(Qn[i] - Qm[i], dt)

Example

VQSUB.dt q0, q1, q2

Encoding

Binary Layout
1111001
U
0
D
size
Vn
Vd
0010
N
0
M
1
Vm
 
Format NEON 3-Reg
Opcode 0xF2000210
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2000210 VQSUB{<c>}{<q>}.<dt> {<Dd>,} <Dn>, <Dm> A32 1111001 | U | 0 | D | size | Vn | Vd | 0010 | N | 0 | M | 1 | Vm
0xF2000250 VQSUB{<c>}{<q>}.<dt> {<Qd>,} <Qn>, <Qm> A32 1111001 | U | 0 | D | size | Vn | Vd | 0010 | N | 1 | M | 1 | Vm
0xEF000210 VQSUB{<c>}{<q>}.<dt> {<Dd>,} <Dn>, <Dm> T32 111 | U | 11110 | D | size | Vn | Vd | 0010 | N | 0 | M | 1 | Vm
0xEF000250 VQSUB{<c>}{<q>}.<dt> {<Qd>,} <Qn>, <Qm> T32 111 | U | 11110 | D | size | Vn | Vd | 0010 | N | 1 | M | 1 | Vm

Description

Vector Saturating Subtract subtracts the elements of the second operand vector from the corresponding elements of the first operand vector, and places the results in the destination vector. Signed and unsigned operations are distinct. The operand and result elements must all be the same type, and can be any one of: If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation occurs. For details see Pseudocode details of saturation. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        for e = 0 to elements-1
            diff = Int(Elem[D[n+r],e,esize], unsigned) - Int(Elem[D[m+r],e,esize], unsigned);
            boolean sat;
            (Elem[D[d+r],e,esize], sat) = SatQ(diff, esize, unsigned);
            if sat then FPSCR.QC = '1';