fminnm

Floating-Point Min Number (Scalar)

FMINNM <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>

Returns smaller value, handling NaNs according to IEEE 754-2008 'minNum'.

Pseudocode Operation

if IsNaN(Vn) then
  result ← Vm
elsif IsNaN(Vm) then
  result ← Vn
else
  result ← min(Vn, Vm)
Vd ← result

Example

FMINNM Dd, Dn, Dm

Encoding

Binary Layout

0

31

0

30

0

29

11110

28:24

00

23:22

1

21

Rm

20:16

01

15:14

11

13:12

10

11:10

Rn

9:5

Rd

4:0

 

Format FP Data Processing

Opcode 0x1E207800

Extension Floating Point

Operands

• Hd|Sd|Dd
  Destination SIMD&FP register (half, single or double-precision)
• Hn|Sn|Dn
  First source SIMD&FP register (half, single or double-precision)
• Hm|Sm|Dm
  Second source SIMD&FP register (half, single or double-precision)

Related

More in Floating Point

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x0EC00400	FMINNM <Vd>.<T>, <Vn>.<T>, <Vm>.<T>		A64		0 | Q | 0 | 01110 | 1 | 10 | Rm | 00 | 000 | 1 | Rn | Rd
0x0EA0C400	FMINNM <Vd>.<T>, <Vn>.<T>, <Vm>.<T>		A64		0 | Q | 0 | 01110 | 1 | sz | 1 | Rm | 11000 | 1 | Rn | Rd
0x1EE07800	FMINNM <Hd>, <Hn>, <Hm>		A64		0 | 0 | 0 | 11110 | 11 | 1 | Rm | 01 | 11 | 10 | Rn | Rd
0x1E207800	FMINNM <Sd>, <Sn>, <Sm>		A64		0 | 0 | 0 | 11110 | 00 | 1 | Rm | 01 | 11 | 10 | Rn | Rd
0x1E607800	FMINNM <Dd>, <Dn>, <Dm>		A64		0 | 0 | 0 | 11110 | 01 | 1 | Rm | 01 | 11 | 10 | Rn | Rd
0xC120A121	FMINNM { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T>		A64		11000001 | size | 10 | Zm | 101000 | 0100 | 1 | Zdn | 1
0xC120A921	FMINNM { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T>		A64		11000001 | size | 10 | Zm | 101010 | 0100 | 1 | Zdn | 0 | 1
0xC120B121	FMINNM { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }		A64		11000001 | size | 1 | Zm | 0101100 | 010 | 0 | 1 | Zdn | 1
0xC120B921	FMINNM { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> }		A64		11000001 | size | 1 | Zm | 00101110 | 010 | 0 | 1 | Zdn | 0 | 1
0x651D8000	FMINNM <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>		A64		01100101 | size | 011 | 10 | 1 | 100 | Pg | 0000 | i1 | Zdn
0x65058000	FMINNM <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>		A64		01100101 | size | 00 | 010 | 1 | 100 | Pg | Zm | Zdn

Description

Floating-point Minimum Number (scalar). This instruction compares the first and second source SIMD&FP register values, and writes the smaller of the two floating-point values to the destination SIMD&FP register. Regardless of the value of FPCR.AH, the behavior is as follows: This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();
bits(esize) operand1 = V[n, esize];
bits(esize) operand2 = V[m, esize];

boolean merge = IsMerging(FPCR);
bits(128) result = if merge then V[n, 128] else Zeros(128);

Elem[result, 0, esize] = FPMinNum(operand1, operand2, FPCR);

V[d, 128] = result;