fcvtx

FCVTX <Zd>.S, <Pg>/M, <Zn>.D

Floating-point Convert to Single (Exact)

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout

01100101

31:24

0010

21:18

101

15:13

12:10

9:5

4:0

Format Float

Opcode 0x650AA000

Extension Float

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x650AA000	FCVTX <Zd>.S, <Pg>/M, <Zn>.D		A64		01100101 \| 0 \| 0 \| 0010 \| 1 \| 0 \| 101 \| Pg \| Zn \| Zd

Description

Convert active double-precision floating-point elements from the source vector to single-precision, rounding to Odd, and place the results in the even-numbered 32-bit elements of the destination vector, while setting the odd-numbered elements to zero. Inactive elements in the destination vector register remain unmodified. Rounding to Odd (aka Von Neumann rounding) permits a two-step conversion from double-precision to half-precision without incurring intermediate rounding errors.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(VL) result = Z[d, VL];

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        bits(esize) element = Elem[operand, e, esize];
        bits(d_esize) res = FPConvertSVE(element<s_esize-1:0>, FPCR, FPRounding_ODD, d_esize);
        Elem[result, e, esize] = ZeroExtend(res, esize);

Z[d, VL] = result;