fadd

Floating-point Add (Double)

FADD <Dd>, <Dn>, <Dm>

Adds two double-precision floating-point registers.

Details

The Floating-point Add instruction adds two double-precision floating-point registers.

Pseudocode Operation

Dd ← Dn + Dm
// Flags affected: N, Z, C, V

Example

FADD d0, d1, d2

Encoding

Binary Layout
00011110
011
Rm
001010
Rn
Rd
 
Format Float Data Proc
Opcode 0x1E602800
Extension F.P.

Operands

  • Dd
    Dest (64-bit)
  • Dn
    First source 64-bit SIMD/FP register
  • Dm
    Second source 64-bit SIMD/FP register