fadd

Floating-point Add (Double)

FADD <Dd>, <Dn>, <Dm>

Adds two double-precision floating-point registers.

Details

Floating-point addition of two double-precision (64-bit) values. Adds operand Dn and operand Dm and writes the result to Dd. FPSR exception flags are updated; condition flags (N, Z, C, V) are unaffected. AArch64-only instruction; uses IEEE 754 rounding mode from FPCR.

Pseudocode Operation

operand1 ← Dn (64-bit float)
operand2 ← Dm (64-bit float)
result ← FPAdd(operand1, operand2)
Dd ← result
UpdateFPSR(exception_flags)

Example

FADD d0, d1, d2

Encoding

Binary Layout
0
0
0
11110
01
1
Rm
001
0
10
Rn
Rd
 
Format Float Data Proc
Opcode 0x1E602800
Extension F.P.

Operands

  • Dd
    Dest (64-bit)
  • Dn
    First source 64-bit SIMD/FP register
  • Dm
    Second source 64-bit SIMD/FP register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0E401400 FADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 0 | 01110 | 0 | 10 | Rm | 00 | 010 | 1 | Rn | Rd
0x0E20D400 FADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 0 | 011100 | sz | 1 | Rm | 11010 | 1 | Rn | Rd
0x1EE02800 FADD <Hd>, <Hn>, <Hm> A64 0 | 0 | 0 | 11110 | 11 | 1 | Rm | 001 | 0 | 10 | Rn | Rd
0x1E202800 FADD <Sd>, <Sn>, <Sm> A64 0 | 0 | 0 | 11110 | 00 | 1 | Rm | 001 | 0 | 10 | Rn | Rd
0x1E602800 FADD <Dd>, <Dn>, <Dm> A64 0 | 0 | 0 | 11110 | 01 | 1 | Rm | 001 | 0 | 10 | Rn | Rd
0x65188000 FADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const> A64 01100101 | size | 011 | 00 | 0 | 100 | Pg | 0000 | i1 | Zdn
0x65008000 FADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 01100101 | size | 00 | 000 | 0 | 100 | Pg | Zm | Zdn
0x65000000 FADD <Zd>.<T>, <Zn>.<T>, <Zm>.<T> A64 01100101 | size | 0 | Zm | 000 | 00 | 0 | Zn | Zd
0xC1A01C00 FADD ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zm1>.<T>-<Zm2>.<T> } A64 110000011 | sz | 1000000 | Rv | 111 | Zm | 00 | 0 | off3
0xC1A41C00 FADD ZA.H[<Wv>, <offs>{, VGx2}], { <Zm1>.H-<Zm2>.H } A64 110000011 | 0 | 1001000 | Rv | 111 | Zm | 00 | 0 | off3
0xC1A11C00 FADD ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zm1>.<T>-<Zm4>.<T> } A64 110000011 | sz | 1000010 | Rv | 111 | Zm | 000 | 0 | off3
0xC1A51C00 FADD ZA.H[<Wv>, <offs>{, VGx4}], { <Zm1>.H-<Zm4>.H } A64 110000011 | 0 | 1001010 | Rv | 111 | Zm | 000 | 0 | off3

Description

Floating-point Add (scalar). This instruction adds the floating-point values of the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register. This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();
bits(esize) operand1 = V[n, esize];
bits(esize) operand2 = V[m, esize];

boolean merge = IsMerging(FPCR);
bits(128) result = if merge then V[n, 128] else Zeros(128);

Elem[result, 0, esize] = FPAdd(operand1, operand2, FPCR);

V[d, 128] = result;