ssra

Signed Shift Right and Accumulate

SSRA <Vd>.<T>, <Vn>.<T>, #<shift>

Arithmetic right shift and add to destination.

Details

Performs an arithmetic (sign-extending) right shift on each source element, then accumulates (adds) the shifted result into the corresponding destination element. No condition flags are modified. This is an AArch64 NEON instruction.

Pseudocode Operation

for i = 0 to elements-1 do
  shifted ← Vn[i] >> shift  (arithmetic shift)
  Vd[i] ← Vd[i] + shifted
endfor

Example

SSRA v0.4s.T, v1.4s.T, #LSL

Encoding

Binary Layout
0
Q
0
011110
immh
immb
00
0
1
01
Rn
Rd
 
Format SIMD Shift Imm
Opcode 0x0F001400
Extension NEON (SIMD)

Operands

  • Vd
    Dest/Acc
  • Vn
    First source SIMD/FP vector register
  • shift
    Imm

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x5F401400 SSRA D<d>, D<n>, #<shift> A64 01 | 0 | 111110 | immh | immb | 00 | 0 | 1 | 01 | Rn | Rd
0x0F001400 SSRA <Vd>.<T>, <Vn>.<T>, #<shift> A64 0 | Q | 0 | 011110 | immh | immb | 00 | 0 | 1 | 01 | Rn | Rd
0x4500E000 SSRA <Zda>.<T>, <Zn>.<T>, #<const> A64 01000101 | tszh | 0 | tszl | imm3 | 1110 | 0 | 0 | Zn | Zda

Description

Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n, datasize];
bits(datasize) operand2;
bits(datasize) result;
integer element;

operand2 = if accumulate then V[d, datasize] else Zeros(datasize);
for e = 0 to elements-1
    element = RShr(Int(Elem[operand, e, esize], unsigned), shift, round);
    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;

V[d, datasize] = result;