sdot

SVE Signed Dot Product

SDOT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>

Computes dot product of signed integers (AI Acceleration).

Details

Computes the dot product of signed integer vectors and accumulates the result into the destination register, supporting AI acceleration. No condition flags are affected. This instruction is AArch64-only and available with the SVE extension; the destination is widened relative to the sources, and the accumulation is added to existing values in Zda.

Pseudocode Operation

for i = 0 to VL/esize_dst-1
  product ← 0
  for j = 0 to (esize_dst / esize_src) - 1
    product ← product + sign_extend(Zn[i*esize_dst + (j+1)*esize_src - 1 : i*esize_dst + j*esize_src], esize_dst) * sign_extend(Zm[i*esize_dst + (j+1)*esize_src - 1 : i*esize_dst + j*esize_src], esize_dst)
  Zda[i+1:i] ← Zda[i+1:i] + product

Example

SDOT z0.s.T, z1.s.Tb, z2.s.Tb

Encoding

Binary Layout
01000100
size
0
Zm
00000
0
Zn
Zda
 
Format SVE Dot Product
Opcode 0x44000000
Extension SVE

Operands

  • Zda
    Accumulator
  • Zn
    First source scalable vector register (SVE)
  • Zm
    Second source scalable vector register (SVE)

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0F00E000 SDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.4B[<index>] A64 0 | Q | 0 | 01111 | size | L | M | Rm | 1110 | H | 0 | Rn | Rd
0x0E009400 SDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> A64 0 | Q | 0 | 01110 | size | 0 | Rm | 1 | 0010 | 1 | Rn | Rd
0x4400C800 SDOT <Zda>.S, <Zn>.H, <Zm>.H A64 01000100000 | Zm | 11001 | 0 | Zn | Zda
0x4480C800 SDOT <Zda>.S, <Zn>.H, <Zm>.H[<imm>] A64 01000100100 | i2 | Zm | 11001 | 0 | Zn | Zda
0x44000000 SDOT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> A64 01000100 | size | 0 | Zm | 00000 | 0 | Zn | Zda
0x44A00000 SDOT <Zda>.S, <Zn>.B, <Zm>.B[<imm>] A64 01000100 | 1 | 0 | 1 | i2 | Zm | 00000 | 0 | Zn | Zda
0x44E00000 SDOT <Zda>.D, <Zn>.H, <Zm>.H[<imm>] A64 01000100 | 1 | 1 | 1 | i1 | Zm | 00000 | 0 | Zn | Zda
0xC1501000 SDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] A64 110000010101 | Zm | 0 | Rv | 1 | i2 | Zn | 0 | 0 | 0 | off3
0xC1509000 SDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] A64 110000010101 | Zm | 1 | Rv | 1 | i2 | Zn | 0 | 0 | 0 | 0 | off3
0xC1601408 SDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H A64 11 | 0000010110 | Zm | 0 | Rv | 101 | Zn | 0 | 1 | off3
0xC1701408 SDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H A64 11 | 0000010111 | Zm | 0 | Rv | 101 | Zn | 0 | 1 | off3
0xC1E01408 SDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } A64 11 | 000001111 | Zm | 00 | Rv | 101 | Zn | 0 | 0 | 1 | off3
0xC1E11408 SDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H } A64 11 | 000001111 | Zm | 010 | Rv | 101 | Zn | 00 | 0 | 1 | off3
0xC1501020 SDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>] A64 110000010101 | Zm | 0 | Rv | 1 | i2 | Zn | 1 | 0 | 0 | off3

Description

The signed integer dot product instruction computes the dot product of a group of four signed 8-bit or 16-bit integer values held in each 32-bit or 64-bit element of the first source vector multiplied by a group of four signed 8-bit or 16-bit integer values in the corresponding 32-bit or 64-bit element of the second source vector, and then destructively adds the widened dot product to the corresponding 32-bit or 64-bit element of the destination vector. This instruction is unpredicated.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(VL) operand1 = Z[n, VL];
bits(VL) operand2 = Z[m, VL];
bits(VL) operand3 = Z[da, VL];
bits(VL) result;

for e = 0 to elements-1
    bits(esize) res = Elem[operand3, e, esize];
    for i = 0 to 3
        integer element1 = SInt(Elem[operand1, 4 * e + i, esize DIV 4]);
        integer element2 = SInt(Elem[operand2, 4 * e + i, esize DIV 4]);
        res = res + element1 * element2;
    Elem[result, e, esize] = res;

Z[da, VL] = result;