ssub16

Signed Subtract 16 (A32)

SSUB16<c> <Rd>, <Rn>, <Rm>

Parallel sub of two signed 16-bit halfwords.

Details

The Signed Subtract 16 instruction parallel sub of two signed 16-bit halfwords.

Pseudocode Operation

Rd ← Rn - Rm
// Flags affected: N, Z, C, V

Example

SSUB16 r0, r1, r2

Encoding

Binary Layout
cond
01100001
Rn
Rd
1111
0111
Rm
 
Format SIMD Integer
Opcode 0x06100F70
Extension A32 (DSP)

Operands

  • Rd
    Destination general-purpose register
  • Rn
    First source / base general-purpose register
  • Rm
    Second source / offset general-purpose register