fmul

Vector Floating-Point Multiply

FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Multiplies elements of floating-point vectors.

Details

Multiplies corresponding floating-point elements in Vn and Vm, storing results in Vd. Supports both 32-bit (sz=0) and 64-bit (sz=1) floating-point lanes across 64-bit (Q=0) or 128-bit (Q=1) vectors. Floating-point exception behavior follows IEEE 754 semantics; no integer condition flags are affected. Executes in AArch64 state with NEON extension.

Pseudocode Operation

if sz == '0' then
  for i = 0 to (datasize / 32) - 1
    Vd[i*32 +: 32] ← FPMul(Vn[i*32 +: 32], Vm[i*32 +: 32], FPCR)
else
  for i = 0 to (datasize / 64) - 1
    Vd[i*64 +: 64] ← FPMul(Vn[i*64 +: 64], Vm[i*64 +: 64], FPCR)

Example

FMUL v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout
0
Q
1
011100
sz
1
Rm
11011
1
Rn
Rd
 
Format SIMD Three Register
Opcode 0x2E20DC00
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x5F009000 FMUL <Hd>, <Hn>, <Vm>.H[<index>] A64 01 | 0 | 11111 | 00 | L | M | Rm | 1001 | H | 0 | Rn | Rd
0x5F809000 FMUL <V><d>, <V><n>, <Vm>.<Ts>[<index>] A64 01 | 0 | 111111 | sz | L | M | Rm | 1001 | H | 0 | Rn | Rd
0x0F009000 FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.H[<index>] A64 0 | Q | 0 | 01111 | 00 | L | M | Rm | 1001 | H | 0 | Rn | Rd
0x0F809000 FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>] A64 0 | Q | 0 | 011111 | sz | L | M | Rm | 1001 | H | 0 | Rn | Rd
0x2E401C00 FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 1 | 01110 | 0 | 10 | Rm | 00 | 011 | 1 | Rn | Rd
0x2E20DC00 FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 1 | 011100 | sz | 1 | Rm | 11011 | 1 | Rn | Rd
0x1EE00800 FMUL <Hd>, <Hn>, <Hm> A64 0 | 0 | 0 | 11110 | 11 | 1 | Rm | 0 | 00010 | Rn | Rd
0x1E200800 FMUL <Sd>, <Sn>, <Sm> A64 0 | 0 | 0 | 11110 | 00 | 1 | Rm | 0 | 00010 | Rn | Rd
0x1E600800 FMUL <Dd>, <Dn>, <Dm> A64 0 | 0 | 0 | 11110 | 01 | 1 | Rm | 0 | 00010 | Rn | Rd
0x651A8000 FMUL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const> A64 01100101 | size | 011 | 01 | 0 | 100 | Pg | 0000 | i1 | Zdn
0x65028000 FMUL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 01100101 | size | 00 | 001 | 0 | 100 | Pg | Zm | Zdn
0x65000800 FMUL <Zd>.<T>, <Zn>.<T>, <Zm>.<T> A64 01100101 | size | 0 | Zm | 000 | 01 | 0 | Zn | Zd
0x64202000 FMUL <Zd>.H, <Zn>.H, <Zm>.H[<imm>] A64 01100100 | 0 | i3h | 1 | i3l | Zm | 0010 | 0 | 0 | Zn | Zd
0x64A02000 FMUL <Zd>.S, <Zn>.S, <Zm>.S[<imm>] A64 01100100 | 1 | 0 | 1 | i2 | Zm | 0010 | 0 | 0 | Zn | Zd

Description

Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    Elem[result, e, esize] = FPMul(element1, element2, FPCR);

V[d, datasize] = result;