tbl
SVE Table Lookup
TBL <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
Looks up elements in a vector table using indices.
Details
SVE Table Lookup performs a vector table lookup where Zn acts as a table and Zm contains indices; Zd receives the looked-up elements. Out-of-range indices produce zero. This operation is element-wise and unpredicated. No condition flags are affected. This is an AArch64-only SVE instruction requiring SVE support.
Pseudocode Operation
Example
TBL z0.s.T, z1.s.T, z2.s.T
Encoding
Binary Layout
00000101
size
1
Zm
001100
Zn
Zd
Operands
-
Zd
Destination scalable vector register (SVE) -
Zn
Table -
Zm
Indices
Reference (Arm A64 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x0E000000 | TBL <Vd>.<Ta>, { <Vn>.16B }, <Vm>.<Ta> | A64 | 0 | Q | 001110 | 00 | 0 | Rm | 0 | 00 | 0 | 00 | Rn | Rd | ||
| 0x0E002000 | TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B }, <Vm>.<Ta> | A64 | 0 | Q | 001110 | 00 | 0 | Rm | 0 | 01 | 0 | 00 | Rn | Rd | ||
| 0x0E004000 | TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B }, <Vm>.<Ta> | A64 | 0 | Q | 001110 | 00 | 0 | Rm | 0 | 10 | 0 | 00 | Rn | Rd | ||
| 0x0E006000 | TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B, <Vn+3>.16B }, <Vm>.<Ta> | A64 | 0 | Q | 001110 | 00 | 0 | Rm | 0 | 11 | 0 | 00 | Rn | Rd | ||
| 0x05203000 | TBL <Zd>.<T>, { <Zn>.<T> }, <Zm>.<T> | A64 | 00000101 | size | 1 | Zm | 001100 | Zn | Zd | ||
| 0x05202800 | TBL <Zd>.<T>, { <Zn1>.<T>, <Zn2>.<T> }, <Zm>.<T> | A64 | 00000101 | size | 1 | Zm | 00101 | 0 | Zn | Zd |
Description
Reads each element of the second source (index) vector and uses its value to select an indexed element from a table of elements consisting of one or two consecutive vector registers, where the first or only vector holds the lower numbered elements, and places the indexed table element in the destination vector element corresponding to the index vector element. If an index value is greater than or equal to the number of vector elements then it places zero in the corresponding destination vector element.
Since the index values can select any element in a vector this operation is not naturally vector length agnostic.
Operation
CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(VL) indexes = Z[m, VL];
bits(VL) result;
constant integer table_size = if double_table then VL*2 else VL;
constant integer table_elems = table_size DIV esize;
bits(table_size) table;
if double_table then
bits(VL) top = Z[(n + 1) MOD 32, VL];
bits(VL) bottom = Z[n, VL];
table = (top:bottom)<table_size-1:0>;
else
table = Z[n, table_size];
for e = 0 to elements-1
integer idx = UInt(Elem[indexes, e, esize]);
Elem[result, e, esize] = if idx < table_elems then Elem[table, idx, esize] else Zeros(esize);
Z[d, VL] = result;