movi

Move Immediate (Vector)

MOVI <Vd>.<T>, #<imm8> {, lsl #<shift>}

Moves an immediate value into every element of a vector.

Details

Moves an 8-bit immediate value into every element of a NEON vector, with optional left shift by 0, 8, 16, or 24 bits. The immediate is replicated across all elements of the destination vector (64-bit or 128-bit depending on Q field). No condition flags are affected. This is an AArch64-only NEON instruction requiring SIMD support.

Pseudocode Operation

shift_amount ← cmode<1:0> * 8
if Q == 0 then
  Vd[63:0] ← replicate(imm8 << shift_amount, element_size)
else
  Vd[127:0] ← replicate(imm8 << shift_amount, element_size)
N ← unaffected; Z ← unaffected; C ← unaffected; V ← unaffected

Example

MOVI v0.4s.T, #16

Encoding

Binary Layout
0
Q
0
0111100000
a
b
c
cmode
0
1
d
e
f
g
h
Rd
 
Format SIMD Modified Imm
Opcode 0x0F000400
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • imm8
    Value

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0F00E400 MOVI <Vd>.<T>, #<imm8>{, LSL #0} A64 0 | Q | 0 | 0111100000 | a | b | c | 1110 | 0 | 1 | d | e | f | g | h | Rd
0x0F008400 MOVI <Vd>.<T>, #<imm8>{, LSL #<amount>} A64 0 | Q | 0 | 0111100000 | a | b | c | cmode | 0 | 1 | d | e | f | g | h | Rd
0x0F000400 MOVI <Vd>.<T>, #<imm8>{, LSL #<amount>} A64 0 | Q | 0 | 0111100000 | a | b | c | cmode | 0 | 1 | d | e | f | g | h | Rd
0x0F00C400 MOVI <Vd>.<T>, #<imm8>, MSL #<amount> A64 0 | Q | 0 | 0111100000 | a | b | c | cmode | 0 | 1 | d | e | f | g | h | Rd
0x2F00E400 MOVI <Dd>, #<imm> A64 0 | 0 | 1 | 0111100000 | a | b | c | 1110 | 0 | 1 | d | e | f | g | h | Rd
0x6F00E400 MOVI <Vd>.2D, #<imm> A64 0 | 1 | 1 | 0111100000 | a | b | c | 1110 | 0 | 1 | d | e | f | g | h | Rd

Description

Move Immediate (vector). This instruction places an immediate constant into every vector element of the destination SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand;
bits(datasize) result;

case operation of
    when ImmediateOp_MOVI
        result = imm;
    when ImmediateOp_MVNI
        result = NOT(imm);
    when ImmediateOp_ORR
        operand = V[rd, datasize];
        result = operand OR imm;
    when ImmediateOp_BIC
        operand = V[rd, datasize];
        result = operand AND NOT(imm);

V[rd, datasize] = result;